1. Presenting: Yaron Yagoda Kobi Cohen DSP SWITCH Digital Systems Laboratory Winter 2002-2003 Supervisor: Isaschar Walter Mid-Term Presentation

2. PROJECT GOALS A.Adjusting hardware architecture according to specific signal processing software dataflow. B.Designing and implementing a flexible topology of communication(using the McBSP Protocol) between several DSPs and the PC.

3. Problem Description DSP Hardware complexity of O(N^2)

4. GENERAL DESCRIPTION DSP PCI CORE PCI BUS DSP -GUI -DRIVER ALTERA FLEX 10KE Switch Matrix

5. BLOCK DIAGRAM DSP ALTERA FPGA PCI CORE McBSP PROTOCOL PCI BUS DSP

6. BLOCK DIAGRAM )for pipelined connection) DSP ALTERA FPGA PCI CORE McBSP PROTOCOL PCI BUS DSP

7. ALTERA DEVELOPMENT CARD

8. McBSP PIN DESCRIPTION PinI/O Description CLKROReceive clock CLKXOTransmit clock DR IReceived serial data DX OTransmitted serial data FSR IReceive frame synchronization FSXOTransmit frame synchronization

9. McBSP SIGNALS

10. FPGA STRUCTURE

11. CONTROL STRUCTURE TO PCI CORE Communication lines Configuration lines

12. THE SWITCH MATRIX The configuration determines for each DSP where to write its data, whether it is another DSP or the pc. The switch matrix is constantly trying to read from each one of the McBSP ports. When it is able to read curtain data it transfers it to another McBSP port according to the data in it’s configuration register.

13. COMUNICATION STRUCTURE

14. MCBSP READ UNIT

15. MCBSP WRITE UNIT

16. THE GUI The GUI gives the user an easy way to cofigure the Switch Matrix. Through the GUI the user can define the connections between the pc and the DSPs. The GUI also allows passing data to each one of the DSPs through the driver.

17. PROJECT STATUS Introduction with the pci core. Implementation of a simple Input/Output program on the Altera card. Studying and implementing the McBSP protocol. Basic implementation of the switch matrix.

18. FUTURE SCHEDULE Until 3.1 : communicating with one DSP. Until 17.1 : implementing configuration and dataflow control and the switch matrix. Until 24.1 : simulation of the whole system. Until 31.1 : writing the driver and GUI. Until 15.2 : testing & debugging. 22.2 : final presentation.