1. FUNCTIONAL OVERVIEW Design a synchronous 4-bit up and down counter Operates at 25MHz on the positive edge of the clock Designed to drive a 10pF capacitive load Latches a valu e at any point by toggling the enable

2. COUNTER DESIGN FLOW COUNTER T_FLIP_FLOP D FLIP_FLOP XOR SCHMITT TRIGGERSUPER BUFFER COMBINATIONAL LOGIC

3. SCHEMATIC

4. COUNTER TESTBENCH

5. LAYOUT

6. SIGNAL FLOW

7. Schmitt Trigger Design Designed For: VTH(LH) of 3V VTH(HL) of 2V VTH(LH ) VTH(HL)

8. Schmitt Layout

9. Schmitt Trigger Validation

10. Super Buffer Design (Assumed 4 stages) Design First Stage Inverter With Symmetric delays Calculate Ratio Wp/Wn For Each Successive Stage: (Where N is the Nth Stage) α^N(Wp/Wn)

11. Test Bench Output

12. French Fried Design I(max) for AL (Metal 1) = 1 x 10^5 A/cm^2 Our Buffer: 5.27 x 10^5 A/cm^2

13. Super Buffer Layout

14. T-Flip Flop Schematic Preset Clear Clock Enable

15. T-Flip Flop Layout

16. T-FF Transient Response

18. H-Tree Clocking Scheme

19. Conclusion 4 Bit Counter with up and down count capability Preset, Clear, Enable Inputs Operates at 25Mhz Clock Frequency with a delay of 6ns from Super Buffer. Input Noise Immunity 2.5V +/- 20% Output power of 60mW Driving 10pF Load Total Area of 406um x 925um = 3.76e-3cm^2