1. Lesson 4: “Just like LEGO” The NAND gate “Reading” CMOS gates Designing CMOS gates

2. Logic

3. Paulo MoreiraGates3 NAND 2-inputs “Gates are inverters in disguise!” “Gates are inverters in disguise!”

4. Paulo MoreiraGates4 NAND 3-inputs

5. Paulo MoreiraGates5 NAND 3-inputs

6. NAND: Switching Time, Propagation Delay t Low2High = R p /N (N*C out, p +C out, n /N+C load ) t High2Low = N*R n (C out, n /N+N*C out, p +C load ) Gate Delay=1/2*(t L2H+ t H2L) n,p : n-channel, p-channel transistors. Rp,Rn: Ron of respective transistors. N = number of Inputs.

7. Estimation of Gate Delay: Gate Delay = K1(pSec) +K2 (pSec*um/fF)* Cload / Wn Wn =Width of n-channel FET (Wp/Wn=constant) K 1 & K 2 determined from spice simulation of cascaded inverters. Wp/WnK1K2 13912.8 2388.78 3416.35 When FETs in series, the effective W is respectively smaller. Cload calculated from Fan-out * Capacity(per Gate) + Capacity of Line.

8. Paulo MoreiraGates8 NAND 3-inputs

9. Paulo MoreiraGates9 NAND 3-inputs

10. Paulo MoreiraGates10 “Reading” CMOS gates

11. Paulo MoreiraGates11 Designing CMOS gates

12. Paulo MoreiraGates12 Complex CMOS gates Can a compound gate be arbitrarily complex? –NO, propagation delay is a strong function of fan-in: –FO  Fan-out, number of loads connected to the gate: 2 gate capacitances per FO + interconnect –FI  Fan-in, Number of inputs in the gate: Quadratic dependency on FI due to: –Resistance increase –Capacitance increase –Avoid large FI gates (Typically FI  4)

13. NAND: Switching Point V SP=(  n / (N*  p))^ 1/2 *VT,n+(VDD-VT,p) -------------------------------------- 1+(  n / (N*  p))^ 1/2 N = number of Inputs. n,p : n-channel, p-channel transistors.