1. SAT Algorithms in EDA Applications Mukul R. Prasad Dept. of Electrical Engineering & Computer Sciences University of California-Berkeley EE219B Seminar : 3 May 2000

2. Outline  The Propositional Satisfiability (SAT) problem  SAT Applications in EDA  Two classical approaches for SAT  Recent Advances  Solving SAT on Boolean networks  Current research & Future directions

3. Outline  The Propositional Satisfiability (SAT) problem  SAT Applications in EDA  Two classical approaches for SAT  Recent Advances  Solving SAT on Boolean networks  Current research & Future directions

4. The Propositional Satisfiability (SAT) problem Given a formula, f : C1C1 C2C2 C3C3 a=b=c=1 (a,b,c) (C 1,C 2,C 3 )   Comprised of a conjunction of clauses   Defined over a set of variables, V   Each clause is a disjunction of literals of the variables V Example : Does there exist an assignment of Boolean values to the variables, V which sets at least one literal in each clause to ‘1’ ?

5. Outline  The Propositional Satisfiability (SAT) problem  SAT Applications in EDA  Two classical approaches for SAT  Recent Advances  Solving SAT on Boolean networks  Current research & Future directions

6. SAT Applications in EDA  Combinational ATPG (stuck-at, bridging, delay faults)  Circuit Delay Computation  FPGA Routing  Logic Synthesis (viz. redundancy removal)  Combinational Equivalence checking  Processor Verification  Bounded Model Checking  Functional vector generation  Crosstalk Noise Analysis  …..

7. Outline  The Propositional Satisfiability (SAT) problem  SAT Applications in EDA  Two classical approaches for SAT  Davis-Putnam, 1960 (Resolution)  Davis-Logemann-Loveland, 1962 ( Backtracking)  Recent Advances  Solving SAT on Boolean networks  Current research & Future directions

8. Simple Backtracking Algorithm for SAT Is_SAT(f, A) { if Check_SAT(f, A) return SAT if Check_UNSAT(f,A) return UNSAT v = Next_Variable(f, A) if Is_SAT(f, (A,v=0)) return SAT if Is_SAT(f, (A,v=1)) return SAT return UNSAT } f,A v f, (A,v=0)f, (A,v=1) Given : CNF formula f(v 1,v 2,..,v k ), and a total order on the variables v 1,v 2,..,v k

9. Backtracking Contd...  Unit Clause Rule : Assign to true the literal in any single literal clauses.  Iterated application of this is called Boolean Constraint Propagation (BCP) v v Pure Literal Rule : Set any unate variables in the aaformula to their appropriate polarity

10. Resolution (Davis-Putnam 1960) Resolve out variable

11. Resolution Contd... Given : CNF formula f(v 1,v 2,..,v k ), and a total order on the variables v 1,v 2,..,v k For each variable ‘v’ in sequence of the total order :   Resolve out variable ‘v’ and add all generated resolvents to a formula   Remove all clauses with variable ‘v’ Ž Ž Iterate, till : þ þ All clauses are resolved out => SAT ý ý Conflicting pair of unit clauses are created => UNSAT

12. Branching Vs Resolution Branching  Linear space (memory) requirements.  Depth-First search of the solution space.  Simplistic though highly redundant. Resolution  Worst case exponential space (memory) req.  Breadth-First search of the solution space.  Simplistic though highly redundant.

13. Outline  The Propositional Satisfiability (SAT) problem  SAT Applications in EDA  Two classical approaches for SAT  Recent Advances  Non-local implications (SOCRATES, TEGUS)  The GRASP algorithm  Recursive Learning  Solving SAT on Boolean networks  Current research & Future directions

14. Recent Advances  Non-local implications (SOCRATES,TEGUS)  Usually performed as a pre-processing step  long implication chains common in SAT on circuits  Avoid repeated work in BCP v The GRASP algorithm (Silva & Sakallah, 1996) u Distinguishing feature : Conflict analysis

15. Main Features of GRASP SAT X k-1 xkxkxkxk xkxkxkxk x2x2x2x2 x2x2x2x2 x1x1x1x1 x1x1x1x1 xjxjxjxj xjxjxjxj  Failure-driven assertions  Non-chronological backtracking Ž Conflict-based equivalence 1 2 3

16. Conflict Analysis: An Example Decision Assignment: Current Assignment:

17. Example Contd: Implication Graph x 2 = 1@6 x 11 = 0@3 x 6 = 1@6 x 5 = 1@6 x 1 = 1@6 x 9 = 0@1 x 4 = 1@6 x 3 = 1@6 x 10 = 0@3  3333 3333 1111 2222 2222 4444 4444 5555 5555 6666 6666

18. Example Contd…. x 7 = 1@6 x 13 = 1@2 x 12 = 1@2 x 8 = 1@6 ```` ```` 9999 9999 9999 7777 7777 8888 x 1 = 0@6 x 9 = 0@1 x 10 = 0@3 x 11 = 0@3 x1x1 5 3 6 Decision Level

19. Recursive Learning  Proposed by Kunz & Pradhan as a general technique for Boolean Reasoning on logic circuits.  Basic idea : Extract common conclusions by examining all possible scenarios of achieving a given objective, upto a restricted degree (recursion depth). common conclusions all possible scenarios restricted degree ------------------------ ------------------------ ------------------------ ------------------------ ------------------------------------------------ Common Inference !!

20. Recursive Learning on CNF Formulas Assignments:

21. Outline  The Propositional Satisfiability (SAT) problem  SAT Applications in EDA  Two classical approaches for SAT  Recent Advances  Solving SAT on Boolean networks  Current research & Future directions

22. Solving SAT on Boolean networks Observation: Topological circuit information is often crucial to the efficient solution of SAT problems posed on logic circuits.  Natural ordering of variables  Grouping of variables to reason about  Natural partitioning of the problem Proposed Solutions :  Solve SAT directly on the network  Augment a conventional SAT solver with a circuit layer (Silva et. al.: CGRASP)  Extended Implication graph (Tafertshofer et. al.)

23. Current Research Efforts  Incremental SAT (Sakallah et. al.)  Pre-processing of SAT formulas (Silva et. al.)  Dedicated Reconfigurable hardware architecutes (Abramovici et. al., Malik et. al.)  Randomized SAT algorithms for EDA applications (Selman & Kautz, Singhal & Burch)  Bounded /Directed Resolution

24. Suggested Reading  J. Marques-Silva and K. A. Sakallah, “GRASP: A Search Algorithm for Propositional Satisfiability,” in IEEE Transactions on Computers, vol. 48, no. 5. pp 506-51, May 1999  J. Marques-Silva and K. A. Sakallah, “Boolean Satisfiability in Electronic Design Automation,” to appear at DAC 2000.  J. Gu, P. W. Purdom, J. Franco, B. W. Wah, “Algorithms for the Satisfiability (SAT) Problem: A Survey,” DIMACS Series in Discrete Mathematics and Computer Science, vol. 35, pp. 19-151, 1997.