1. Noise Canceling in 1-D Data: Presentation #5 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Feb 21 st, 2005 Component Layout Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics ( almost Done) To be done: –Layout (20%) –Spice simulation

3. Top Level Schematics

4. Revised Floorplan Aspect Ratio = 1:1

5. Component Layout Sine ROM Table/Cosine (Similar) Dimension : 7.8 x 62

6. ROM Controller

7. Mux 2-1

8. Half Adder

9. Full Adder

10. 16 bit 2-1 Mux

11. Last week’s challenges… Completing and Testing Top level Schematic (98% done) Creating Layouts for Floating Point Multipliers and Adders with different shapes. –For Wallace Tree, decided to split it into two trees, incorporating Booth encoding. Clock Skew and other Timing issues – Don’t have to worry about it Transistor count .. again.. –Ok..

12. This week’s challenges… Completing and Testing Top level Schematic –Power Saving options?? Wallace Tree Layout –Is Booth encoding only for 2’s complement numbers?? Functional Blocks Layout –Follow the Floorplan

13. Questions?