1. Split Compilation for Accelerator-based Multicores Panagiotis Theocharis Computer Systems Lab (CSL) Ghent University

2. Problem Statement Ever increasing performance and power-efficiency needs ASICs/ASIPs are becoming unaffordable Heterogeneous concurrency

3. Accelerator-based Multicores General purpose cores Specialized accelerators Interfacing

4. Virtualizing the HW/SW Interface Reuse legacy code Auto-tune for efficiency Immune to hardware innovation Flexible resource allocation

5. Our approach: Split Compilation Static Phase Dynamic Phase Dynamic Phase bytecode code executable annotations Architecture description Offline Time-consuming analyses Hardware-independent optimizations Install/Load/Run time Quick decisions Actual code mapping

6. Target Hardware Platform Two functional views/operation modes Features heterogeneous FUs, local RFs, direct connections between FUs Reconfigurable every cycle Tightly coupled to control processor IMEC ADRES CGRA Coarse-Grained Reconfigurable Array

7. Phase 1 (current) OpenIMPACT DRESC IR architecture description LLVM Heuristical back-end Low Level Virtual Machine compiler infrastructure Replace existing simulated-annealing-based backend Quick decision based on heuristics Depends on code/hardware features Parameterizable for DSE C code ADRES executable

8. Phase 2: Design Space Exploration LLVM DRESC + IR architecture description M achine L earning Design Space Exploration optimized architecture description optimized architecture description optimized compiler strategy C code ADRES executable

9. Phase 3: Virtualization LLVM LLVM – DRESC C code ADRES executable bytecode optimized architecture description deployment time compiler strategy static

10. ML Phase 4: Mapping Automation LLVM LLVM – DRESC bytecode deployment time abstract architecture description optimized architecture description compiler strategy C code static ADRES executable

11. Phase 5: True Split Compilation LLVM LLVM – DRESC bytecode staticdeployment time optimized architecture description compiler strategy ML abstract architecture description annotations C code ADRES executable

12. Split Compilation for Accelerator-based Multicores Panagiotis Theocharis Computer Systems Lab (CSL) Ghent University