1. Emerging Standards in the Electronic Design Automation (EDA) Industry Phil Fisher (SEMATECH) Don Cottrell (Si2) UC Berkeley October 20, 1999

2. 10/20/99 Emerging Standards - at UCB - 2 SEMATECH/International SEMATECH 14 global semiconductor companies: AMDIntel ConexantLucent Technologies Compaq (Digital)Motorola Hewlett-PackardPhilips HyundaiSTMicroelectronics IBMTexas Instruments Infineon TechnologiesTSMC Mission: The members of International SEMATECH will gain a manufacturing advantage through cooperative work on semiconductor manufacturing technology Technical programs cover a broad range of advanced and tactical projects, focusing on wafer processing

3. 10/20/99 Emerging Standards - at UCB - 3 International SEMATECH 14 Firms Cooperating

4. 10/20/99 Emerging Standards - at UCB - 4 25-30% per Year Improvement Time Logarithmic $ per Function Wafer Size Yield Improvement Other Productivity Equipment, etc. Feature Size ~12%-14% ~4% ~2% ~7%-10% ~12% ~8% ~5% ~3% Manufacturing Cost Present ? Keeping Productivity on Track

5. 10/20/99 Emerging Standards - at UCB - 5 We Face Several Non-Incremental Technology Changes Post-optical lithography Copper Low-k dielectrics New gate stacks with deposited dielectrics and metal electrodes 300 mm Plus all the incremental changes — increasing scale of integration, etc. Time Manufacturing Cost Logarithmic $ per Function 2000 25% - 30% per Year Improvement Two decades of incremental change One-decade of non-incremental change

6. 10/20/99 Emerging Standards - at UCB - 6 Design Productivity Crisis Year Technology Chip Complexity Frequency Staff Staff Cost* 1997 1998 1999 2002 250 nm 180 nm 130 nm 13 M Tr. 20 M Tr. 32 M Tr. 130 M Tr. 400 500 600 800 90 M 120 M 160 M 360 M * @ $150K / Staff Yr. (In 1997 Dollars) 210 270 360 800 3 Yr. Design Potential Design Complexity and Designer Productivity 1 10 100 1,000 10,000 100,000 1,000,000 10,000,000 198119831985198719891991199319951997199920012003200520072009 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Logic Tr./Chip Tr./S.M. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip (M) 0.01 0.1 1 10 100 1,000 10,000 100,000 Productivity (K) Trans./Staff - Mo. Equivalent Added Complexity

7. 10/20/99 Emerging Standards - at UCB - 7 Interconnect Complexity

8. 10/20/99 Emerging Standards - at UCB - 8 CHDStd Standard Chip Hierarchical Design System technical date (CHDStd) Standard Why? To help integrate tools into the IC design flow by using a common data model and APIs –For every $1 invested in EDA tools, an additional 2 to $5 are spent on integration into the design flow –No EDA vendor or using company can supply all the tools needed today –Promote rapid integration of new tools from industry and university research –EDA tool supplier integration and maintenance costs

9. 10/20/99 Emerging Standards - at UCB - 9 CHDStd Programs in SEMATECH Working with Leading EDA Suppliers –Interface EDA Tools to CHDStd Contracts with IBM, Cadence, OEA, and Ultima –User Support of CHDStd IBM contract for Implementation Support of data model, API server, and data repository for: –Members, selected EDA suppliers, and Universities Si2 contract for public web site, Test Lab, and standards accreditation in IEEE & IEC Comprehensive Data Types –Libraries, interconnect modeling, ECO, and broaden to behavioral view