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Shift Registers Lecture L6.6 Section 7.3
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4-Bit Shift Register
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shift4.abl MODULE shift4 TITLE '4-bit Shift Register' DECLARATIONS " INPUT PINS " CLK PIN 70; " push-button switch (clock) clear PIN 11; " Switch S6:1 data_in PIN 1; " Switch S7:4 " OUTPUT PINS " Q3..Q0 PIN 40,41,43,44 ISTYPE 'reg buffer'; " LED 13..16 Q = [Q3..Q0]; " 4-bit output vector
![shift4.abl MODULE shift4 TITLE 4-bit Shift Register DECLARATIONS INPUT PINS CLK PIN 70; push-button switch (clock) clear PIN 11; Switch S6:1 data_in PIN 1; Switch S7:4 OUTPUT PINS Q3..Q0 PIN 40,41,43,44 ISTYPE reg buffer ; LED Q = [Q3..Q0]; 4-bit output vector](http://images.slideplayer.com./16/5174715/slides/slide_3.jpg "shift4.abl MODULE shift4 TITLE 4-bit Shift Register DECLARATIONS INPUT PINS CLK PIN 70; push-button switch (clock) clear PIN 11; Switch S6:1 data_in PIN 1; Switch S7:4 OUTPUT PINS Q3..Q0 PIN 40,41,43,44 ISTYPE reg buffer ; LED Q = [Q3..Q0]; 4-bit output vector")
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shift4.abl (cont’d) EQUATIONS Q.AR = clear; Q.C = CLK; Q3.D = data_in; Q2.D = Q3; Q1.D = Q2; Q0.D = Q1;
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@radix 16; test_vectors([CLK, clear, data_in] -> Q) [.C.,1,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; END shift4.abl (cont’d)
![@radix 16; test_vectors([CLK, clear, data_in] -> Q) [.C.,1,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; END shift4.abl (cont’d)](http://images.slideplayer.com./16/5174715/slides/slide_5.jpg "@radix 16; test_vectors([CLK, clear, data_in] -> Q) [.C.,1,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; [.C.,0,1] -> 8; [.C.,0,0] -> 4; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; [.C.,0,1] -> 0A; [.C.,0,0] -> 5; [.C.,0,0] -> 2; [.C.,0,0] -> 1; [.C.,0,0] -> 0; END shift4.abl (cont’d)")
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shift4 simulation
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Ring Counter
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ring4.abl MODULE ring4 TITLE '4-bit Ring Counter' DECLARATIONS " INPUT PINS " CLK PIN 70; " push-button switch (clock) start PIN 11; " Switch S6:1 " OUTPUT PINS " Q3..Q0 PIN 40,41,43,44 ISTYPE 'reg buffer'; " LED 13..16 Q = [Q3..Q0]; " 4-bit output vector Q31 = [Q3..Q1];" upper 3 bits
![ring4.abl MODULE ring4 TITLE 4-bit Ring Counter DECLARATIONS INPUT PINS CLK PIN 70; push-button switch (clock) start PIN 11; Switch S6:1 OUTPUT PINS Q3..Q0 PIN 40,41,43,44 ISTYPE reg buffer ; LED Q = [Q3..Q0]; 4-bit output vector Q31 = [Q3..Q1]; upper 3 bits](http://images.slideplayer.com./16/5174715/slides/slide_8.jpg "ring4.abl MODULE ring4 TITLE 4-bit Ring Counter DECLARATIONS INPUT PINS CLK PIN 70; push-button switch (clock) start PIN 11; Switch S6:1 OUTPUT PINS Q3..Q0 PIN 40,41,43,44 ISTYPE reg buffer ; LED Q = [Q3..Q0]; 4-bit output vector Q31 = [Q3..Q1]; upper 3 bits")
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ring4.abl (cont’d) EQUATIONS Q31.AR = start;" asynchronous reset Q0.AP = start;" asynchronous preset Q.C = CLK; Q3.D = Q0; Q2.D = Q3; Q1.D = Q2; Q0.D = Q1; 0 0 0 1 start = 1
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@radix 16; test_vectors([CLK, start] -> Q) [.C.,1] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; END ring4.abl (cont’d)
![@radix 16; test_vectors([CLK, start] -> Q) [.C.,1] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; END ring4.abl (cont’d)](http://images.slideplayer.com./16/5174715/slides/slide_10.jpg "@radix 16; test_vectors([CLK, start] -> Q) [.C.,1] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; [.C.,0] -> 8; [.C.,0] -> 4; [.C.,0] -> 2; [.C.,0] -> 1; END ring4.abl (cont’d)")
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ring4 simulation
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Ring Counter
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Johnson Counter
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Exercise Detect input sequence 1101 fsm din dout clk clr din dout 1 0 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0
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Use Shift Register CLK DQ !QCLK DQ !QCLK DQ !QCLK DQ !Q CLK Q3Q2Q1Q0 1011 dout din
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A Random Number Generator
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Q3 Q2 Q1 Q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1 1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1 5 Q3 Q2 Q1 Q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0 1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1
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