1. 1 Evgeny Bolotin – ICECS 2004 Automatic Hardware-Efficient SoC Integration by QoS Network on Chip Electrical Engineering Department, Technion, Haifa, Israel Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny QNoC Research Group, Electrical Engineering Department Technion – Israel Institute of Technology Haifa, Israel

2. 2 Evgeny Bolotin – ICECS 2004 Outline Introduction: SoC Integration Challenge NoC Concept and QNoC Architecture SoC Automatic Integration by QNoC Summary

3. 3 Evgeny Bolotin – ICECS 2004 The Integration Challenge: Growing Chip Density 1998 Asic - 0.35  m 2004 SoC – 90 nm Memory, I/O P Design complexity - High IP reuse Scalable and Efficient, High Performance Interconnect Integration Challenge

4. 4 Evgeny Bolotin – ICECS 2004 The Growing Gap: Computation vs. Communication From ITRS, 2001

5. 5 Evgeny Bolotin – ICECS 2004 Traditional SoC Nightmare Variety of dedicated interfaces Poor separation between computation and communication. Design and Verification Complexity Unpredictable performance

6. 6 Evgeny Bolotin – ICECS 2004 Solution – Network on Chip (NoC) Scalability Concurrency, effective spatial reuse of resources Higher bandwidth Higher levels of abstraction Modularity – Productivity Improvement Easier SoC Integration!

7. 7 Evgeny Bolotin – ICECS 2004 NoC vs. “Off-Chip” Networks What is Different? Routers on Planar Grid Topology Short PTP Links between routers Unique VLSI Cost Sensitivity: Area-Routers and Links Power

8. 8 Evgeny Bolotin – ICECS 2004 NoC vs. “Off-Chip Networks” No legacy protocols to be compliant with … No software  simple and hardware efficient protocols Different operating env. (no dynamic changes and failures) Custom Network Design – You design what you need! Replace Example1: Replace modules

9. 9 Evgeny Bolotin – ICECS 2004 NoC vs. “Off-Chip Networks” Example2: Adapt Links Adapt Links Example3: Trim Unnecessary (ports, buffers, routers, links)

10. 10 Evgeny Bolotin – ICECS 2004 QNoC: QoS NoC Define Service Levels (SLs): Signaling Real-Time Read/Write (RD/WR) Block-Transfer Different QoS for each SL

11. 11 Evgeny Bolotin – ICECS 2004 QNoC Architecture Mesh Topology Fixed shortest path routing (X-Y) Simple Router (no tables, simple logic) No deadlock scenario Power efficient communication Wormhole Routing For reduced buffering

12. 12 Evgeny Bolotin – ICECS 2004 QNoC Wormhole Router Input Port Output Port

13. 13 Evgeny Bolotin – ICECS 2004 SoC development with QNoC System Architecture Definition System Integration and Verification

14. 14 Evgeny Bolotin – ICECS 2004 Integration Automation Tools QNoC Placement and Topology Generation Analyzes System Modules and Traffic Derives NoC Topology and Module Placement Minimizes Spatial Traffic Density  For Lower Area and Power

15. 15 Evgeny Bolotin – ICECS 2004 Integration Automation Tools QNoC Customization Maze-Router – for efficient packet routing Link Load Calculator – for capacity allocation QNoC Network Simulator – for QoS assuring Placed ModulesRelative Link Load Simulated QoS

16. 16 Evgeny Bolotin – ICECS 2004 Integration Automation Tools Automatic Hardware Generation Use calculated QNoC parameters and QNoC VHDL templates library Create Synthesizable VHDL description of QNoC Including Module wrappers Synchronization and SER/DES circuitry Routing logic and tables System Verification QNoC verification models For hardware and system simulations

17. 17 Evgeny Bolotin – ICECS 2004 Summary SoC Integration Challenge NoC Concept QNoC Architecture SoC Integration by QNoC Automatic Integration Tools

18. 18 Evgeny Bolotin – ICECS 2004 More Info: www.ee.technion.ac.il/qnoc