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Team M1 Enigma Machine Milestone 9 - 3 April, 2006 Design Manager: Prateek Goenka Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka
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Status Finished: –Behavioral Verilog and C simulation –Structural Verilog –Logic optimization –Module-level spice delay and power simulations –Floorplan –Top-level schematic testing In Progress: –Functional block layout –Simulation of functional blocks To do: –Global Layout –Testing –Simulation STATUS
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Layout done:Layout Needed: GatesROM Muxes and RegistersRAM DFF, TFF FlipflopsFSM Add_Mod26 Wheel Counter Cells Wheel Counter Serial input 3-bit and 5-bit registers
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Design Decisions Layout of Serial in registers Layout of 3-bit and 5-bit counter cells Updated layout of Wheel Counter Floorplan
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Initial Floorplan
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UPDATED FLOORPLAN
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reg3bx8serialin
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reg3bx8_serialin
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Wheelregs_serialin
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Wheel Counter Plan (Module layout and wire planning) 5-bit Counter Cell Data from counters Wheel Select Wheel Position 5-bit Counter Cell
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countunit
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wheelcounter
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Questions?
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