1. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 1 Nitin Yogi and Dr. Vishwani D. Agrawal Auburn University Department of ECE Auburn, AL 36849, USA N-Model Tests for VLSI Circuits

2. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 2 Outline  Multiple fault models Importance Minimization problem  Proposed Multiple Fault Model Test Minimization Obtain Fault Dictionary Solve Integer Linear Program (ILP)  Proposed Combined ILP model ILP Model Results  Hybrid LP-ILP method Algorithm Results  Conclusion

3. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 3 Principle of Testing Circuit under test Input patterns Output responses Comparator Database 011….101 101….100 ……….… 100….001 01….01 …….… 10….11 11….00 Expected correct output responses Test Results Circuit Pass/Fail ? …….…

4. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 4 Physical Defects in VLSI chips Polysilicon bridge between two transistor gates. (Reference: EE times, Article: “Good bridge testing needed” by Greg Aldrich and Brady Benware) Electrical open connection (Reference: Alex A. Volinsky et. al. “FIB failure analysis of memory arrays,” Microelectronic Engineering, Vol. 75, Issue 1, pp 3-11, July 2004.)

5. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 5 Some Example Fault Models A B Stuck-at 0 fault Stuck-at fault model Fault-free value Faulty value Transition delay fault model Slow-to-rise fault A B Fault-free value Faulty value

6. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 6 Multiple Fault Models  Importance Each fault model targets specific defects  Sematech study (Nigh et. al. VTS’97) concluded … To detect most defects, tests for all fault models need to included Combine test sets covering different fault models  Concatenating test sets - number of vectors grows rapidly  Minimization problem Obtain minimized test set for considered fault models  Take advantage of vectors detecting faults in multiple fault models Fault simulator/ATPG handles only one fault model at a time  Need for a new minimization approach

7. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 7 Conventional Test Vector Minimization (one fault model at a time) CircuitType of vecs Mentor Fastscan vectors Fault Cov. (%) Un-minimizedMinimized c3540 Stuck-at 16713096.00 I DDQ (pseudo stuck-at) 534599.09 Transition delay 29922996.55 Total 519404- s5378 Stuck-at 15014599.30 I DDQ (pseudo stuck-at) 717085.75 Transition delay (LOS) 31929398.31 Transition delay (LOC) 25624290.05 Total 796750-

8. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 8 Multiple Fault Model Test Minimization  Obtain fault dictionary by fault simulations Determine faults detected by each vector  ‘F’ faults : for all considered fault models  ‘N’ vectors : generated for all considered fault models  T est minimization by Integer Linear Program (ILP) Set of integer variables Set of constraints Objective function

9. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 9 Combined ILP  Define two [0, 1] integer variables: { t j, i j } – for each vector ; j = 1 to N  t j = 0 : drop vector j  t j = 1 : select vector j  i j = 0 : no I DDQ measurement for vector j  i j = 1 : measure I DDQ for vector j

10. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 10 Combined ILP (cont.)  Constraints {c k } for k th fault, k = 1 to F For k th fault detected by vectors u, v and w c k : t u + t v + t w ≥ 1 i u + i v + i w ≥ 1 t u ≥ i u t v ≥ i v t w ≥ i w Only if k th fault is an I DDQ fault

11. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 11 Combined ILP (cont.)  Objective function Minimize { ∑ t j + W × ∑ i j }  N : total number of vectors  t j : variables to select vectors  i j : variables to select I DDQ measurements  W : weighting factor, W ≥ 0 How strongly to minimize I DDQ vectors (May depend on the relative cost of current measurement) j = 1 N N

12. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 12 Results – Combined ILP Ckt. No. of vecs. & I DDQ meas. W = 0.1W = 1W = 10 Vecs & I DDQ meas. CPU $ (s) Vecs & I DDQ meas. CPU $ (s) Vecs & I DDQ meas. CPU $ (s) c3540 Vecs225 5044* 226 5047* 247 5047* I DDQ 404137 s5378 Vecs320 2314 326 5154* 353 5161* I DDQ 787364 * CPU time limit of 5000 s exceeded $ SUN Sparc Ultra 10, four CPU machine with 4.0 GB shared RAM Need for reducing CPU times

13. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 13 Hybrid LP – ILP  Approximate solution to ILP  Algorithm: 1.All variables redefined as real [0,1] real variables (LP model) 2.Loop : 1.Solve LP 2.Round variables {t j }, {i j } and add as additional constraints 1.Round to 0 if ( 0.0 < variables ≤ 0.1) 2.Round to 1 if ( 0.9 ≤ variables < 1.0) 3.Exit loop if no variables are rounded 3.Reconvert variables to [0,1] integers and solve ILP

14. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 14 Results - Hybrid LP - ILP minimization Ckt. No. of vecs. & I DDQ meas. Combined ILP model ILP solutionHybrid LP – ILP solution W = 0.1W = 1W = 10W = 0.1W = 1W = 10 Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) Vecs / I DDQ CPU $ (s.) c3540 Vecs 225 5044* 226 5047* 247 5047* 225 167 226 189 248 516 I DDQ 404137413934 s5378 Vecs 320 2314 326 5154* 353 5161* 320 529 326 617 353 793 I DDQ 787364807263 * CPU time limit of 5000 s exceeded $ SUN Sparc Ultra 10, four CPU machine with 4.0 GB RAM shared among 4 CPUs Order of magnitude reduction in CPU time

15. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 15 How Good is Hybrid Optimization? CircuitWeight (W) Minimized (vectors + W x IDDQ measurements) Lower BoundILPHybrid LP – ILP c35400.1227.94229*229.1 1257.82267*265 10499.97617*588 s53780.1326.76327.8328 1392.28399*398 10910.68993*983 * CPU time limit of 5000 s exceeded

16. March 17, 2008Southeastern Symposium on System Theory (SSST) 2008, March 16-18, New Orleans, Louisiana 16 Conclusion  Proposed technique Minimizes test vectors for multiple fault models Minimizes I DDQ measurements. Cost Trade-off  Vector Length and I DDQ measurements  Hybrid LP – ILP procedure reduces time complexity of the solution