1. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Basic fabrication steps n Transistor structures n Basic transistor behavior

2. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Fabrication services n Educational services: – U.S.: MOSIS – EC: EuroPractice – Taiwan: CIC – Japan: VDEC n Foundry = fabrication line for hire.

3. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR -based design n is the size of a minimum feature. n Specifying particularizes the scalable rules. n Parasitics are generally not specified in units. n In our 0.5 micron process, =0.25 microns.

4. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Fabrication processes n IC built on silicon substrate: – some structures diffused into substrate; – other structures built on top of substrate. n Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) n Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). n Silicon dioxide (SiO 2 ) is insulator.

5. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Photolithography Mask patterns are put on wafer using photo- sensitive material:

6. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub substrate

7. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps, cont Pattern polysilicon before diffusion regions: p-tub poly gate oxide

8. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps, cont Add diffusions, performing self-masking: p-tub poly n+ p+

9. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Process steps, cont Start adding metal layers: p-tub poly n+ p+ metal 1 vias

10. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Transistor structure n-type transistor:

11. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR 0.25 micron transistor (Bell Labs) poly silicide source/drain gate oxide

12. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Transistor layout n-type (tubs may vary): w L

13. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Drain current characteristics

14. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR 0.5  m transconductances From a 0.5 micron process: n n-type: – k n ?= 73  A/V 2 – V tn = 0.7 V n p-type: – k p ?= 21  A/V 2 – V tp = -0.8 V

15. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Current through a transistor Use 0.5  m parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. n V gs = 2V: I d 0.5k?W/L)(V gs -V t ) 2 = 93  A n V gs = 5V: I d = 1 mA

16. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Basic transistor parasitics n Gate to substrate, also gate to source/drain. n Source/drain capacitance, resistance.

17. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Basic transistor parasitics, cont n Gate capacitance C g. Determined by active area. n Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. – C gs = C ol W n Gate/bulk overlap capacitance.

18. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Latch-up n CMOS ICs have parastic silicon-controlled rectifiers (SCRs). n When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. n Early CMOS problem. Can be solved with proper circuit/layout structures.

19. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Parasitic SCR circuit

20. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Parasitic SCR structure I-V behavior

21. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

22. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Tub tie layout metal (V DD ) p-tub p+

23. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Body effect n Reorganize threshold voltage equation: V t = V t0 +  V t n Threshold voltage is a function of source/substrate voltage V sb. Body effect  is the coefficienct for the V sb dependence factor.

24. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR The modern MOSFET Features of deep submicron MOSFETs: –epitaxial layer for heavily-doped channel; –reduced area source/drain contacts for lower capacitance; –lightly-doped drains to reduce hot electron effects; –silicided poly, diffusion to reduce resistance.

25. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Circuit simulation n Circuit simulators like Spice numerically solve device models and Kirchoff laws to determine time-domain circuit behavior. n Numerical solution allows more sophisticated models, non-functional (table- driven) models, etc.

26. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Spice MOSFET models n Level 1: basic transistor equations of Section 2.2; not very accurate. n Level 2: more accurate model (effective channel length, etc.). n Level 3: empirical model. n Level 4 (BSIM): efficient empirical model. n New models: level 28 (BSIM2), level 47 (BSIM3).

27. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Some (by no means all) Spice model parameters L, W : transistor length width. KP : transconductance. GAMMA : body bias factor. AS, AD : source/drain areas. CJSW : zero-bias sidewall capacitance. CGBO : zero-bias gate/bulk overlap capacitance.

28. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Topics n Wire and via structures n Wire parasitics n Transistor parasitics

29. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Wires and vias p-tub poly n+ metal 1 metal 3 metal 2 vias

30. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Metal migration n Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. n Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

31. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Metal migration problems and solutions n Marginal wires will fail after a small operating period : infant mortality. n Normal wires must be sized to accomodate maximum current flow: I max = 1.5 mA/  m of metal width. n Mainly applies to V DD /V SS lines.

32. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Diffusion wire capacitance n Capacitances formed by p-n junctions: n+ (N D ) depletion region substrate (N A ) bottomwall capacitance sidewall capacitances

33. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Poly/metal wire capacitance n Two components: –parallel plate; –fringe. plate fringe

34. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Metal coupling capacitances n Can couple to adjacent wires on same layer, wires on above/below layers: metal 2 metal 1

35. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Example: parasitic capacitance measurement n n-diffusion: bottomwall=2 fF, sidewall=2 fF. n metal: plate=0.15 fF, fringe=0.72 fF. 3  m 0.75  m 1  m 1.5  m 2.5  m

36. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Wire resistance n Resistance of any size square is constant:

37. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Transistor gate parasitics n Gate-source/drain overlap capacitance: gate sourcedrain overlap

38. Modern VLSI Design 2e: Chapter 2 Copyright  1998 Prentice Hall PTR Transistor source/drain parasitics n Source/drain have significant capacitance, resistance. n Measured same way as for wires. n Source/drain R, C may be included in Spice model rather than as separate parasitics.