1. SecurOne - Design Presentation
Group M1
Insik Yoon
Mehul Jain
Sriteja Tangeda
Umang Shah
Monday 21st September
Behavioral Verilog, Signals and Initial Estimates
Secure unique Smart Card and Card Reader

2. Status Finished: To Do: Design selections Block diagram for processes
Behavioral Verilog (Individual modules done. Testing??)
Floorplan (v rough bound to change in future)
To Do:
Schematic
Layout
Testing
Simulation

3. Card Insert Block Reader
Smart Card
write_card
choice_data_SC
encrypted_data
data_tobdecrypted
read_datafromSC
data_arrivedfromcard 1 5 16 16 1 1
Card Insert Block Reader
card_insert 1
display_menu 1
SecurOne
Display Unit USER
data_todisplay
cardread_data 16 16
display_data 1
card_read 1
choice_made 1
user_choice
FPread_data 16 5
Finger Print Reader
display_data 1
Display Unit VENDOR
data_todisplay
FP_read 1 16
data_FP
choice_data_CS
data_encrypted
data_arrivedfromCS 5 16 16 1
Central Server

4. SRAM 4 BYTE Finger Print Data
Initial FSM Flow Chart
Control Unit Initial
Card Reader B 1
Finger Print Reader B 1 A 1 G C 16 1 D C 1 1 1 1 C E
Decryptor 16 E 16
Comp
SRAM 4 BYTE Finger Print Data F 16 F 16 F

5. Signals for Initial FSM
Signal Name
Length
Operation A
Card_insert
1 bit
Card Reader Control_Unit B
Card_read
Control_Unit Card Reader
FP_read
Control_Unit FP_Reader C
Card read_data
16 bit
Card Reader Decryptor
FPread_data
FP_Reader SRAM Write Driver 2
Write_FPSRAM2
Control_Unit WE2 D
Decryption_complete
Decryption Control_Unit E
Decrypted_Data
Decryption SRAM Write Driver 1
Write_FPSRAM1
Control_Unit WE1 F
FSM_compare
Control_Unit SRAM Read 1 & 2
Read_FP_CMP1
SRAM Comparator
Read_FP_CMP2 G
Compare_Result
Comparator Control Unit

6. Control Unit Initial A 1 B 1
Display Unit User
Main Menu FSM 2 C
C={00}
Control Unit Update
Control Unit Display
Control Unit Trans.
Control Unit Exit

7. SRAM 4 BYTE Finger Print Data Control Unit Update
Update FSM Flow Chart H 5
Main Menu FSM
Smart Card H 16 I 1 1 J
Display Unit User A 1
SRAM 4 BYTE Finger Print Data
Control Unit Update B 1 D 1 1 5 D G C 1 H 1 C 1
SRAM 5Bit (Choice Regfile) F 16 E
Central Server Interface 5 E G
Encryptor 16

8. SIGNALS FOR UPDATE FSM Signal Signal Name Length Operation A
Display_menu
1 bit
Update CU Display Unit B
Choice_made
Display Unit Update CU C
write_choice
Update CU Choice Regfile
User_choice
5 bits
Display unit Choice Regfile D
Read_choice
Update CU Choice Regfile
Read_FP SRAM
Update CU FP_SRAM E
Choice_data_CS
5 bit
Choice Regfile Central Server
Data_FP
16 bit
FP_SRAM Central Server F
Data_arrived from CS
Central Sever Update CU G
Data_encyrption
Central Sever Encryptor
Update CU Choice Regfile H
Encrypted_Data
Encryptor Smart Card
Choice_data_SC
Choice Regfile Smart Card
Encryption_done
Encryptor Update CU I
Write_Card
Update CU Smart Card J
Reset
Update CU Main-Menu CU

9. B
Display Unit User
Main Menu FSM 1 2 C
C={01}
Control Unit Update
Control Unit Display
Control Unit Trans.
Control Unit Exit

10. SRAM 5Bit (Choice Regfile)
Display FSM Flow Chart
Main Menu FSM I J 1 16 K 1 I 1
Control Unit Display A 1
SRAM 2 BYTE Display Data
Display Unit User 1 B 1 H D 1 G 5 16 1 E F C 1 C
SRAM 5Bit (Choice Regfile) H 1 1
Decryptor
Smart Card 16 E 5 F

11. SIGNALS FOR DISPLAY FSM
Signal Name
Length
Operation A
Display_menu
1 bit
Display CU Display Unit B
Choice_made
Display Unit Display CU C
write_choice
Display CU Choice Regfile
User_choice
5 bits
Display unit Choice Regfile D
Read_choice E
Choice_data
5 bit
Choice Regfile Smart Card
Read_DatafromSC
1bit
Display CU Smart Card F
Data_arrived from Card
Smart Card Display CU
Data_tobedecrypted
16 bit
Smart Card Decryptor G
Decryption_Complete
Decryptor Display CU H
Decrypted_Data
Decryptor Display SRAM
Write_data
Display CU Display SRAM I
Data_toDisplay
Display SRAM Display Unit
Read_Data
Display CU Display SRAM J
Display_Data
Display CU Display Unit K
Reset
Display CU Main-Menu CU

12. B
Display Unit User
Main Menu FSM 1 2 C
C={10}
Control Unit Update
Control Unit Display
Control Unit Trans.
Control Unit Exit

13. Transaction FSM Flow Chart
Display Unit Vendor
Main Menu FSM I 16 1 J 1 K
Control Unit Trans. A 1 I
SRAM 2 BYTE Transaction Data
Display Unit User 1 B 1 H 1 D C C F 1 G 1 5 E 1 1 16
SRAM 5Bit (Choice Regfile) H 1
Decryptor
Smart Card 16 F E 5

14. SIGNALS FOR TRANSACTION FSM
Signal Name
Length
Operation A
Get_info_vendor
1 bit
Trans CU Display Unit B
Info_received
Display Unit Trans CU C
write_choice
Trans CU Choice Regfile
User_choice
5 bits
Display unit Choice Regfile D
Read_choice E
Choice_data
5 bit
Choice Regfile Smart Card
Read_DatafromSC
TransCU Smart Card F
Data_arrived from Card
Smart Card Trans CU
Data_tobedecrypted
16 bit
Smart Card Decryptor G
Decryption_Complete
Decryptor Trans CU H
Decrypted_Data
Decryptor Trans SRAM
Write_data
Trans CU Trans SRAM I
Data_toDisplay
Trans SRAM Display_Unit_Ven
Read_Data
Trans CU Trans SRAM J
Display_Data
Trans CU Display_Unit_Ven K
Reset
Trans CU Main-Menu CU

15. B
Main Menu FSM 1
Display Unit User
Control Unit Initial 2 C
C={11}
Control Unit Update
Control Unit Display
Control Unit Trans.
Control Unit Exit

16. FLOOR-PLAN Exit Initial FSM Main Menu FSM Decryptor 4 B SRAM
Display_menu 2
Exit
choice
Initial FSM
Main Menu FSM
exit W1 W2 R1 R2
Compare_result 2 1
return
Decryptor
4 B SRAM
Update FSM
choice
Decryption_complete R1
FP_1 16
FP_2 1
Comparator 2 16
Display FSM
choice
Decrypted_Data
Write
Choice Regfile
Read
Read
Write
Encryptor 1
encryption_complete
Display SRAM 2B
Write
Trans. FSM 2
Read
choice
Trans. SRAM 2B
Write
Read

17. Encryption/Decryption
Transistor Counts
Block
Transistor Count
Encryption/Decryption
8000
FSMs (Still Unsure??)
5000
SRAMs
1000
Comparator
200

18. ENCRYPTION ALGORITHM RC4
Generates a pseudo random stream of bits (a key stream) which for encryption is combined with the plain text using bitwise XOR
Implemented scaled down version with encryption key length = 16 bits

19. RC_4 key_init
module rc4_init(input clk, input start, input [15:0] key, output reg [63:0] S, output reg ready) ; reg start_reg; reg [3:0] j; reg [3:0] S_reg[15:0]; reg [3:0] tmp; reg [5:0] loc0, loc1; reg init_reg; integer i; begin for( i=0; i<16; i=i+1)begin S_reg[i] = i; end j=4'b0000; start_reg = start; end (start_reg) begin for( i=0; i< 16; i=i+1)begin j = (j+key[i]+S_reg[i])&4'b1111; tmp = S_reg[i]; S_reg[i]=S_reg[j]; S_reg[j] = tmp; // $display("S_reg: %h complete:%h key:%h j:%h i:%h start:%h", S_reg[i], init_reg, key,j,i,start); end init_reg = 1; end ( init_reg)begin S ={ S_reg[15], S_reg[14], S_reg[13], S_reg[12], S_reg[11], S_reg[10], S_reg[9], S_reg[8], S_reg[7], S_reg[6], S_reg[5], S_reg[4], S_reg[3], S_reg[2], S_reg[1], S_reg[0]}; ready =1'b1; //$display("S: %h ready:%h", S, ready); end endmodule  

20. RC4_keygen
// $display ("S_out: %h i:%h j:%h tmp:%h tmp1:%h", S_out[3:0], i,j,tmp,tmp1); i=(i+1)&4'b1111; tmp = S_reg[i]; j= (j+ tmp)&4'b1111; S_reg[i]= S_reg[j]; S_reg[j] = tmp; tmp1 = (S_reg[i]+S_reg[j])&4'b1111; S_out[11:8]= S_reg[tmp1]; // $display ("S_out: %h i:%h j:%h tmp:%h tmp1:%h", S_out[3:0], i,j,tmp,tmp1); i=(i+1)&4'b1111; tmp = S_reg[i]; j= (j+ tmp)&4'b1111; S_reg[i]= S_reg[j]; S_reg[j] = tmp; tmp1 = (S_reg[i]+S_reg[j])&4'b1111; S_out[15:12]= S_reg[tmp1]; // $display ("S_out: %h i:%h j:%h tmp:%h tmp1:%h", S_out[3:0], i,j,tmp,tmp1); complete_reg=1; end (posedge clk & complete_reg) begin S_key<=S_out; ready<=1; //$display ("S_out: %h S_key:%h", S_out, S_key); end endmodule  
module rc4_keygen(input [63:0] S,input clk, input init, output reg[15:0] S_key, output reg ready); reg [3:0] i,j,tmp,tmp1; reg [3:0] S_reg[15:0]; reg [15:0] S_out; reg init_reg; reg complete_reg; i=0; j=0; S_reg[0] = S[3:0]; S_reg[1] = S[7:4]; S_reg[2] = S[11:8]; S_reg[3] = S[15:12]; S_reg[4] = S[19:16]; S_reg[5] = S[23:20]; S_reg[6] = S[27:24]; S_reg[7] = S[31:28]; S_reg[8] = S[35:32]; S_reg[9] = S[39:36]; S_reg[10]= S[43:40]; S_reg[11]= S[47:44]; S_reg[12]= S[51:48]; S_reg[13]= S[55:52]; S_reg[14]= S[59:56]; S_reg[15]= S[63:60]; init_reg = 1; end (init_reg) begin i=(i+1)&4'b1111; tmp = S_reg[i]; j= (j+ tmp)&4'b1111; S_reg[i]= S_reg[j]; S_reg[j] = tmp; tmp1 = (S_reg[i]+S_reg[j])&4'b1111; S_out[3:0]= S_reg[tmp1]; //$display ("S_out: %h i:%h j:%h tmp:%h tmp1:%h", S_out[3:0], i,j,tmp,tmp1); i=(i+1)&4'b1111; tmp = S_reg[i]; j= (j+ tmp)&4'b1111; S_reg[i]= S_reg[j]; S_reg[j] = tmp; tmp1 = (S_reg[i]+S_reg[j])&4'b1111; S_out[7:4]= S_reg[tmp1];

21. RC4_encrypt
module rc4_encrypt( input [15:0] val, input [15:0] key,input start, input clk,output reg[15:0] encrypt,output reg complete); wire [63:0] S; wire init_complete; wire [15:0] scram_key; wire keygen_complete; rc4_init init(.clk(clk),.start(start),.key(key), .S(S), .ready(init_complete)); rc4_keygen keygen (.clk(clk),.init(init_complete), .S(S), .S_key(scram_key), .ready(keygen_complete)); (posedge clk & keygen_complete)begin encrypt= val^scram_key; #5 complete=1; end endmodule  

22. RC4_decrypt
module rc4_decrypt( input [15:0] encrypt, input [15:0] key,input start, input clk,output reg[15:0] val,output reg complete); wire [63:0] S; wire init_complete; wire [15:0] scram_key; wire keygen_complete; rc4_init init(.clk(clk),.start(start),.key(key), .S(S), .ready(init_complete)); rc4_keygen keygen (.clk(clk),.init(init_complete), .S(S), .S_key(scram_key), .ready(keygen_complete)); ( keygen_complete)begin $display("keygen:%h", keygen_complete); val= encrypt^scram_key; complete = 1; end endmodule  

23. RC4_encrypt testbench
module test_encrypt(); reg [15:0] data; reg [15:0] key; reg start; reg clk; wire [15:0] encrypt; wire complete; always #2 begin clk = ~clk; end rc4_encrypt en(.val(data), clk(clk), start(start), key(key), encrypt(encrypt), complete(complete)); initial begin $monitor($time, "data:%h, clk:%h start:%h key:%h, encrypt:%h complete:%h", data, clk, start, key, encrypt, complete); clk = 0; data = 16'h8894; key = 16'b ; start =1; #20 data = 16'h53f2; key = 16'b ; #20 data = 16'h1e64; key = 16'b ; #200; $stop; end endmodule  

24. RC4_decrypt testbench
module test_decrypt(); reg [15:0] encrypt; reg [15:0] key; reg start; reg clk; wire [15:0] val; wire complete; always #2 begin clk = ~clk; end rc4_decrypt decrypt(.encrypt( encrypt), clk(clk), start(start), key(key), val(val), complete(complete)); initial begin $monitor($time, "encrypt:%h, clk:%h start:%h key:%h, val:%h complete:%h", encrypt, clk, start, key, val, complete); clk = 0; encrypt = 16'b ; key = 16'b ; start =1; #10 encrypt = 16'b ; key = 16'b ; #10 encrypt = 16'b ; key = 16'b ; #10; $stop; end endmodule  

25. Rc4 encrypt waveform

26. RC4 decrypt waveform

27. RC 4 – Really Testable with the entire Circuit?
if(start) begin for( i=0; i<16; i=i+1)begin S_reg[i] = i; end j=4'b0000; start_reg = start; end if(start_reg)begin for( i=0; i< 16; i=i+1)begin j = (j+key[i]+S_reg[i])&4'b1111; tmp = S_reg[i]; S_reg[i]=S_reg[j]; S_reg[j] = tmp; end init_reg = 1; end
Given is the verilog code for the key generation
ONLY!!!!
4 Bit Addition – 16 Times
16 clock cycles
Swapping Operation: 3 Read and 3 Writes per swapping operation
6 Clock Cycles per Swap
In Total 16*6 = 96 Clock Cycles

28. RC 4 – Really Testable with the entire Circuit?
if(start) begin for( i=0; i<16; i=i+1)begin S_reg[i] = i; end j=4'b0000; start_reg = start; end if(start_reg)begin for( i=0; i< 16; i=i+1)begin j = (j+key[i]+S_reg[i])&4'b1111; tmp = S_reg[i]; S_reg[i]=S_reg[j]; S_reg[j] = tmp; end init_reg = 1; end
Total = = 112 Clock Cycles for generating the 16 bit key!!!!

29. Hardware Implementation
Swapping Operation
S[0]
Swapping of S[0] with S[1]
STEP 1: Read S[0]
STEP 2: Write 0 in Temp
STEP 3: Read S[1]
STEP 4: Write 1 in 0
STEP 5: Read Temp
STEP 6: Write Temp in 1
Hardware:
Generating Addresses for all the registers.
Decoding the Addresses .
Generating the control signals for all the read/write operations.
S[1]
S[2]
S[3]
S[14]
S[15]
Temp

30. Hardware Implementation
Adder
Add operation will have to be implemented using two – 4 bit Addition (j =j+key[i]+S_reg[i])
Thus this operation will also require a temporary register to hold the intermediate results, in addition to the 32 (2*16 : 16 more than that estimated using the behavioral verilog code) clock cycles .

31. Alternatives We go for TEA (Tiny Encryption Algorithm)
May not be the best and the safest but…..