1. Lecture 23 Performance, Slide 1EECS40, Fall 2004Prof. White Lecture #23 Performance OUTLINE Timing diagrams (from Lecture 22) Delay analysis (from Lecture 22) Maximum clock frequency - three figures of merit Continuously-switched inverters Ring oscillators Reading (Rabaey et al.) Parts of Ch. 5: Pages 179-184; 193-203; 212-217; 220- 227; 230-232 Perspective and Summary

2. Lecture 23 Performance, Slide 2EECS40, Fall 2004Prof. White AF Propagation Delay in Timing Diagrams To simplify the drawing of timing diagrams, we can approximate the signal transitions to be abrupt (though in reality they are exponential). t A 1 0 t F 1 0 t pHL t pLH To further simplify timing analysis, we can define the propagation delay as

3. Lecture 23 Performance, Slide 3EECS40, Fall 2004Prof. White Glitching Transitions The propagation delay from one logic gate to the next can cause spurious transitions, called glitches, to occur. (A node can exhibit multiple transitions before settling to the correct logic level.) A B C F t A,B,C 1 0 0 t B 1 B BC A+BA+B t 1 0 t 1 0 A+B t 0 1 F tptp 2tp2tp 3tp3tp

4. Lecture 23 Performance, Slide 4EECS40, Fall 2004Prof. White Glitch Reduction Spurious transitions can be minimized by balancing signal paths Example: F = ABCD

5. Lecture 23 Performance, Slide 5EECS40, Fall 2004Prof. White MOSFET Layout and Cross-Section Top View: Cross Section:

6. Lecture 23 Performance, Slide 6EECS40, Fall 2004Prof. White Source and Drain Junction Capacitance C source = C j  (AREA) + C jsw  ( PERIMETER) = C j L S W + C JSW (2L S + W)

7. Lecture 23 Performance, Slide 7EECS40, Fall 2004Prof. White Computing the Output Capacitance In Out Metal1 V DD GND Poly-Si PMOS W/L=9 /2 In Out Example 5.4 (pp. 197-203) NMOS W/L=3 /2 2 =0.25  m

8. Lecture 23 Performance, Slide 8EECS40, Fall 2004Prof. White In Out V DD GND PMOS W/L=9 /2 NMOS W/L=3 /2 2 =0.25  m Capacitances for 0.25  m technology: Gate capacitances: C ox (NMOS) = C ox (PMOS) = 6 fF/  m 2 Overlap capacitances: CGDO(NMOS) = C on = 0.31fF/  m CGDO(PMOS)= C op = 0.27fF/  m Bottom junction capacitances: CJ(NMOS) = K eqbpn C j = 2 fF/  m 2 CJ(PMOS) = K eqbpp C j = 1.9 fF/  m 2 Sidewall junction capacitances: CJSW(NMOS) = K eqswn C j = 0.28fF/  m CJSW(PMOS) = K eqbpp C j = 0.22fF/  m

9. Lecture 23 Performance, Slide 9EECS40, Fall 2004Prof. White

10. Lecture 23 Performance, Slide 10EECS40, Fall 2004Prof. White Typical MOSFET Parameter Values For a given MOSFET fabrication process technology, the following parameters are known: –V T (~0.5 V) –C ox and k (<0.001 A/V 2 ) –V DSAT (  1 V) –  (  0.1 V -1 ) Example R eq values for 0.25  m technology (W = L):

11. Lecture 23 Performance, Slide 11EECS40, Fall 2004Prof. White Compute propagation delays

12. Lecture 23 Performance, Slide 12EECS40, Fall 2004Prof. White Examples of Propagation Delay Product CMOS technology generation Clock frequency, f Fan-out=4 inverter delay Pentium II 0.25  m 600 MHz~100 ps Pentium III 0.18  m 1.8 GHz~40 ps Pentium IV 0.13  m 3.2 GHz~20 ps Typical clock periods: high-performance  P: ~15 FO4 delays PlayStation 2: 60 FO4 delays

13. Lecture 23 Performance, Slide 13EECS40, Fall 2004Prof. White STATIC CMOS DRIVING LARGE LOADS We have seen that the typical driving resistance R for a minimum sized inverter is in the range of 10 K . A 1 K  resistor driving a 50pF load would have a stage delay of 35nsec, huge in comparison to normal stage delays. The load, C L, may be the capacitance of a long line on the chip (e.g. up to 1pF, or may be the load on one of the chip output pins (e.g. up to 50pF). v out v in + - V DD MN 1 MP 1 CLCL Thus we need to use larger devices to drive large capacitive loads, that is greatly increase W/L. However, increasing W/L of a stage will increase the load it presents to the stage driving it, and we just move the delay problem back one stage.

14. Lecture 23 Performance, Slide 14EECS40, Fall 2004Prof. White STATIC CMOS DRIVING LARGE LOADS CLCL PROPOSED SOLUTION: Insert several simple inverter stages with increasing W/L between Inverter 1 and the load C L. The total delay through the multiple stages will be less than the delay of one single stage driving C L. PROBLEM: A minimum sized inverter drives a large load, C L, leading to excessive delay, even with a buffer stage. v in + - V DD MN 1 MP 1 v out V DD MN B MP B

15. Lecture 23 Performance, Slide 15EECS40, Fall 2004Prof. White STATIC CMOS DRIVING LARGE LOADS Example: The 2.5V 0.25  m CMOS inverter driving 50 pF load. Properties: W/L| N =1/.25, W/L| P =2/.25, V DD = 2.5V, V T = 0.5V. Rn = 13 K  K  Rp = 31 K  K   5nm oxide thickness, C ox =6.9 fF/  m 2. NMOS: C Gp = W x L x C ox =1.7 fF. PMOS : C Gp = W x L x C ox =3.4 fF. Thus C IN = 5.2 fF Thus the gate delay for the first stage is (50000/5.2)X10pS = 96.1nS. Total delay = 96.1 +.01 = 96.11nS. TOO LONG and NO IMPROVEMENT! W/L = 4 W/L = 9615 Basic gate delay (0.69RC) is about 10pS. If we size one inverter to drive the load with this time constant it requires a W/L increase by a factor of 50pF/5.2fF =9615. So C IN = 50000fF =50pF for the buffer gate! Note: We are ignoring drain capacitance in these examples. v in + - V DD MN 1 MP 1 v out MN B MP B 50 pF

16. Lecture 23 Performance, Slide 16EECS40, Fall 2004Prof. White STATIC CMOS DRIVING LARGE LOADS Same example with tapered device sizes (geometric series) Case 2: Now taper through 3 buffer stages with W/L ratios of 9.9 (9.9 4 =9615) Case 1: Same example, but with buffer devices scaled by factor of 98 (98 2 =9615 ) Stage 1 load = 98 X 5.2fF, (R= 3.5K) Stage 2 load = 50 pF, (R = 3.5K /98) Delay = 98 X 10pS + 96nS/98 =0.98 +0.98 nS ~2nS 4 equal gate delays of 9.9 x 10pS =99pS Total = 4 X.099nS ~0.4nS Gate delay through 4 gates is much less than through 2! Note: We are ignoring drain capacitance in these examples.

17. Lecture 23 Performance, Slide 17EECS40, Fall 2004Prof. White STATIC CMOS DRIVING LARGE LOADS Comments In our example we got better results with 3 buffer stages than 1. 7 buffer stages would do even better. How many buffer stages are optimum? Well under these simple assumptions (like ignoring drain and wiring capacitance, and operating asynchronously) you can show that the number of buffer stages, N obeys N +1 = ln(R) where R is the ratio of the load capacitance to the capacitance of a minimum sized stage. This formula is not important, but you should remember the concept that buffering with multiple stages usually leads to lower net delay if the load is large. v out v in + - CLCL V DD MN 1 MP 1 MN B1 MP B1 MN B2 MP B2 MN B3 MP B3

18. Lecture 23 Performance, Slide 18EECS40, Fall 2004Prof. White How to measure inverter performance? 2) The stage delay when the input is a continuous square-wave clock input. v out1 =v in2 v in1 + - V DD MN 1 MN 2 MP 3 MP 4 There are two other measures of performance which we can also consider: 1) We have defined the unit delay  t p as the time until V out1 reaches V DD /2 starting at either 0V (rising) or V DD (falling). V in1 is a step function. 3) The delay of a pulse through a multi-stage “ring oscillator”,

19. Lecture 23 Performance, Slide 19EECS40, Fall 2004Prof. White Unit gate delay performance measurement t Suppose V in1 goes from low to high. The properly designed stage will have similar delay time for rising input as for falling input. (Design proper ratio of W p to W n ) V v out1 =v in2 v in1 + - V DD MN 1 MN 2 MP 3 MP 4 V DD Because when it reaches this value, the following stage will sense that its input has switched from high to low. Similarly t pLH is the time for the output to rise from zero to V DD /2 when the input is falling. V out1 goes from V DD to ground. We defined the inverter delay t pHL as the time until V out1 reaches V DD /2. tptp 0.5 V DD Maximum frequency is just 1/(t pHL + t pLH 

20. Lecture 23 Performance, Slide 20EECS40, Fall 2004Prof. White Driving Inverters (or gates) with Square-Wave Clock 1/f V DD In   Node X loaded by C X Inverter 1 has output resistance R p or R n Output slowly converges to sawtooth waveform. Let’s find relationship between max and min values v h and v l after many many cycles: (1) Pull down: (2) Pull up: Example: can solve simultaneously given  t/RC t1t1 t4t4 t3t3 t2t2 t5t5 etc. V IN, V X Lets follow V X for V IN starting at t=0 VlVl VhVh

21. Lecture 23 Performance, Slide 21EECS40, Fall 2004Prof. White Square-Wave Drive 1/f V DD In  Inverter 2 will operate correctly so long as V X passes through v il and v ih. We approximate response of devices in inverter 2 as instantaneous (remember the steep transfer curve). Let’s look at V X after a long time. ih V il V When V X crosses down through v il, inverter 2 switches, and when it crosses up through v ih, it switches back t1t1 t4t4 t3t3 t2t2 t5t5 etc.

22. Lecture 23 Performance, Slide 22EECS40, Fall 2004Prof. White If frequency increases when will inverter fail? If V X does not pass through V il or V ih, because frequency is too high. MAXIMUM CLOCK FREQUENCY f max : Increase f until inverter 2 fails to toggle because its input does not pass through its threshold(s). In general, R p  R n, so rise or fall is slower.

23. Lecture 23 Performance, Slide 23EECS40, Fall 2004Prof. White Example: Now consider the square-wave drive case: Take V DD =2.5V, V ih = 1.5, V il = 1V, so in this symmetric case: CΔt/R DDilDDih CΔt/R ihil p n )eV-V(V vand eVv    Solving either equation with RC = 15pS,  t = 6.1pS; f max2 = 10 12 /12.2=82GHz (obviously this result depends on our somewhat arbitrary choice for V ih and V il ) Take R = 3 K, C = 5 fF, t pHL = t pLH = 0.69 RC = 10pS ; So f max1 = 50GHz ih V il V

24. Lecture 23 Performance, Slide 24EECS40, Fall 2004Prof. White Ring Oscillator As soon as the inverter 1 drives inverter 2’s input past V il (falling) or V ih (rising), inverter 2 switches and starts driving input node of  toward its switch point, etc. Result: Signal propagates along chain at another kind of maximum clock frequency f max * (really maximum propagation frequency ) Odd number of stages Let the average delay per stage be  t MIN then the time around loop is N   t MIN. One period is twice around the loop, so, something very easy to measure. [ If  t MIN is 20pSec but N is 1001, the period 1/ f RO is 40 nSec.] easy to measure (low frequency) could be 1001 123n … 4 Now we. define f max * by,so Note: V starts at 0V (rising) or VDD (falling) WHY? NOTE: f max *< f max2 WHY?

25. Lecture 23 Performance, Slide 25EECS40, Fall 2004Prof. White Ring Oscillator As soon as the switch closes inverter 5 drives inverter 1’s input up (starting at 0 V). When it reaches V ih inverter 1 switches and starts driving input node of inverter two down, starting at V DD.. We note that the transient always starts at 0 or V DD and ends at V ih or V il, respectively. This clearly takes longer than the clock-driven chain of inverter transient. Need to solve same exponential equations as in square-wave drive, but with different limits: Up: Start at 0, end at V ih. Down: Start at V DD, end at V il. V ih = V DD [1-exp(-  t LH /R p C)] V il = V DD [exp(-  t HL /R n C)] Solve for  t LH and  t HL and avg. to get  t MIN :  t MIN = (  t LH +  t HL )/2 Odd number of stages 0=0V101 1=V DD 0 close switch

26. Lecture 23 Performance, Slide 26EECS40, Fall 2004Prof. White Ring Oscillator Example From V ih = V DD [1-exp(-  t LH /R p C)] we find  t LH = 13.7pS Similarly from V il = V DD [exp(-  t HL /R n C)]  t HL = 13.7pS Thus the delay through 101 stages, twice is 202 X 13.7 =2.78nS. The ring oscillator frequency is 10 9 /2.78 = 360 MHz. Finally, f max * = 360 X 101 = 36 GHz. This is of course less than either the 50GHz estimated from unit gate delay or the 82 GHz estimated from square-wave driven max toggle frequency. 101 Stages, same parameters: (RC = 15 pS) 0=0V101 1=V DD 0 close switch