1. DSI Division of Integrated Systems Design No switch fabric required Highlights: Access and edge routers Applications: Truly output queuing Highly integrated Low implementation cost Up to 32x32 OC-48 ports Dedicated physical link between I/O ports Zero loss of traffic with no redundancy schemes Two-chip set Sophisticated QoS with 16 programmable classes of traffic Highly efficient support for end-to-end flow control Full Unicast and Multicast support Proven high-speed 3Gbps multidrop serial link structure Enterprise backbone switch Gigabit ethernet 3G wireless gateway Storage area networking GMDS line card Gigabit MultiDrop Switch (GMDS) CSIX compatible I/O interface Line card features: GMDS line card integrates advanced queuing (Queue Manager, QM) and scheduling (Scheduler, SC) functions in a two-chip set architecture. QM manages up to 4 lines from multidrop backplane, storing incoming frames in a high capacity external RAM, and maintaining information about memory usage. SC selects data to be dequeued according to different scheduling algorithms and traffic configuration from QM.  Up to 16 programmable weighted classes of traffic and 4 end-to-end programmable flow control levels supported.  The number of QM devices depends on desired number of supported ports.  Proven Low-cost line card prototype supporting 8 ports GMDS Diagram Line Card Architecture The Gigabit MultiDrop Switch (GMDS) is a low-cost, high performance switch based on a feasible real output queue architecture. GMDS is based on a two-chip set architecture and a proven high-speed multidrop backplane with dedicated links between I/O ports, which avoid the need for switch fabrics. The GMDS architecture supports sophisticated QoS at the egress ports, which enhance scheduling algorithms effectiveness. Unicast and Multi/Broadcast variable packet size frames are inherently supported for the multidrop backplane, enabling the system for a high efficient bandwidth usage. Ports in GMDS can be scaled in any size from 4x4 to 32x32 OC-48.

2. DSI Division of Integrated Systems Design Gigabit MultiDrop Switch (GMDS) Eye diagram @3 Gbps Jitter measurement @3 Gbps Gigabit multidrop backplane Trully output queuing architecture is allowed by the multidrop backplane solution. However, traditional stubs result in signal integrity degradation in multidrop backplanes at high-speed, which implies that maximum data- rate on commercial multidrop backplanes is limited to 400 Mbps. Patent Pending Our new developed multidrop serial link structure based on power splitters with matching trace impedance is demonstrated to operate @ 3 Gbps. Gigabit Multidrop Backplane GMDS Features About DSI The Division of Integrated Systems Design is composed of experienced researchers who are developing commercial products and doing outstanding private and public research in the field of microelectronics since late 80s. The strength of the team is based on its know-how, cutting-edge resources and a set of services which permit to fulfill your company requirements, increasing its competitiveness and international position in new challenging markets. For more information on DSI’s Gigabit MultiDrop Switch, please contact: dsi@iuma.ulpgc.es © 2004 Division of Integrated Systems Design IUMA Universidad de Las Palmas de Gran Canaria Campus Universitario de Tafira Las Palmas de Gran Canaria, SPAIN Tel: +34 928451232 (direct) +34 928451250 (reception desk) Fax: +34 928451243 URL: www.iuma.ulpgc.es