1. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino VLSI electronics for the read-out of radiation sensors Angelo Rivetti – INFN - Torino

2. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Topics  Introduction  Architectures for read-out ASICs  Why deep submicron CMOS?  A detailed example: the ALICE SDD front-end

3. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Why integrated ?  Historically, dedicated integrated circuits came into play in nuclear electronics with the advent of silicon detectors.  Nowadays they are used to read-out most radiation detectors, including gas detectors  The possible use of APDs as an alternative to PMTs further increase the range of application of custom integrated I.Cs.  The use of I.Cs is motivated by the need of reading many channels minizing material and power consumption

4. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino The LHC scale The LHC detectors need an unprecedented number of electronics channels…

5. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino ALICE Silicon pixels: 0.2 m 2, 9.3Mch Silicon drift: 1.3m 2, 133kch Silicon strip: 4.9m 2, 2.6Mch TPC: Volume 88m 3, 1Mch … and many others…

6. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino ATLAS & CMS In term of number of channels, ALICE is dwarfed by ATLAS & CMS CMS 210m 2 silicon microstrip sensors 9.6 Mch ATLAS 61m 2 silicon microstrip sensors 6.3 Mch

7. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino A detector example You have to read-out something like this….(SDD of ALICE) Many independent channels have to be read

8. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Basic design choices From system specs to Selection of the architecture System partitioning Technology choice

9. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Architecture selection (1) Analog read-out +  No info loss  Amplitude preserved  Easier to debug S&H -  Big amount of data  Analog data handling Very common for the read-out of silicon microstrip

10. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Analog read-out example The APV chip for the CMS tracker 128 analog channels Preamp & analog pipeline Analog deconvolution processor CMOS 0.25  m technology 46.8 mm 2 2mW/channel Reference: L.L Jones et al. The APV25 Deep Submicron ReadOut Chip http://lebwshop.home.cern.ch/lebwshop/LEB99_ Book/Tracker/Jones.pdf

11. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Architecture selection (2) Binary read-out +  Simple  Fast  Minimum amount of data -  No information on amplitude  More difficult to debug V TH Standard for the read-out of pixel detectors Common also for strip detectors

12. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Binary read-out example The ABCD chip for the ATLAS microstrip 128 channels Preamp & discriminator Digital pipeline 46.8 mm 2 2mW/ch BiCMOS 0.8  m rad-hard Reference: W. Dabrowski et al. Design an performance of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker IEEE TNS, vol. 47, no. 6, Dec. 2000

13. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Architecture selection (3) Mixed-mode readout +  No information loss  Robust -  Large data volume  Mixed-mode IC more difficult to design We will see more on this later… ADC

14. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Mixed-mode readout example The ALTRO chip for the ALICE TPC 16 ADC Embedded digital processing Digital tail cancellation CMOS 0.25  m technology 64 mm 2 16mW/ch @ 10 MSPS Preamp on a separate IC Reference: R. Esteve Bosch, L. Musa, et. al The ALTRO chip: A 16 Channel A-D converter and digital processor for Gas Detectors IEEE NSS – MIC, Norfolk, Nov. 2002.

15. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Why deep-submicron CMOS ? CMOS already popular in the design of front-end v noise 2 C t 2 K 2 (n) ENC 2 = i noise 2 K 1 (n)  s + ss Bipolar traditionally better at short shaping time, due to the base current shot noise

16. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Process trends in CMOS technologies

17. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Interconnection example

18. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Digital vs analog  The scaling of CMOS technologies is driven by the need of improving the perfomance of digital ICs  The need of analog design not taken too much into account  Analog features come usually later  Digital circuits improve with scaling, but what about analog ones?

19. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Analog properties and process scaling: (1) t OX scales, k=  Cox =  OX /t OX scales => for the same W /L and the same current gm improves Lmin (  m) tox (nm) k (  A/V 2 ) 1.22468 0.81490 0.510134 0.255280 k for different technologies (NMOS devices) gmgm = 2 nn C OX W L I DS This is for strong inversion…

20. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Analog properties and process scaling: (2) k=  Cox scales => for the same W and L:  W.I.-S.I. boundary moves towards higher currents: I lim =2nk(W/L)U T 2 g m /I DS max in W.I.

21. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Analog properties and process scaling (3) t ox scales => C ox and k=  C ox increase. For the same W and L:  matching improves:  flicker noise is reduced:  transconductance increases: S V K a C WLf ox 2 

22. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino 0 Vdd VTp Vdd-VTn gds Vdd=5V 0 Vdd Vdd-VTn VTp gds Vdd=1.6V ck ck_b Vin Problem: SC circuits operation (1)

23. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino W/L=200/0.36 C L =20pF f in =2.5MHz ck ck_b Vin CLCL Problem: SC circuits operation (2)

24. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Problem: substrate noise P+ P- digital analog

25. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Analog properties and process scaling: (3) t ox scales => Vdd must be scaled as well Minimum power consumption for class A analog circuits:  V is the fraction of the power supply not used for signal swing

26. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Analog properties : summary  Transistor properties improve, but signal swing is reduced => is there an optimum?  Optimal power/performance trade-off may occur with 0.35 - 0.25  m! (A. J. Annema, IEEE Trans. On Cicuits and Systems, II vol 46, No. 6, June 1999).   In 0.25  m CMOS (2.5V) conventional architectures still work!

27. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Effect of radiation on MOS (1)  The sensitive part is the oxide  A ionizing particle creates electron- hole pairs  In the oxide, the mobility of holes is much smaller than the one of electrons (7-12 orders of magnitude)  Three main effects arise: => threshold shift of the main device => threshold shift of parasitic devices => interface state generation SiO 2 n+ gate P- n+

28. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Effect of radiation on MOS (2)

29. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Effect of radiation on MOS (3) polisilicon nwell n+ Vdd Vss source ++++++++++ Inter-device leakage via thick oxide

30. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Rad-tol design approach S D G D S G Thin oxide + enclosed layout & guardring (ELT) = radiation tolerance Deep submicron CMOS is a good choice for rad-tol IC for HEP Single Event Effect may worsen, but... Extesively studied by the CERN RD49 collaboration

31. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Silicon Drift Detector (SDD) Drift of charged particles in silicon 2-dimension measurement 20  m resolution dE/dx measurement with analog read-out “few” read-out channel drift speed 5  m/ns but…v=  E,   T -2.4 !

32. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino.....

33. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino  Total number of channels: 130000  Input charge 500e- to 250000e-  Input signal: Gaussian (amplitude 10nA - 1.6  A;  10ns – 30ns)  Shaping time: 40ns  Sampling frequency: 40 MS/s  Bits/sample: 10  Noise < 500 e- rms (250e- rms)  Power/channel < 5mW  Front-end board: 8 x 2 cm 2  System dead time: < 1ms  Reduce material as much as possible SDD system specifications

34. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino  On the front-end board space for 8 VLSI chips  Optimize the system for minimum output connections  Preamplifier  Sampling: 1 FADC/channel: impractical for power and space  First level analog buffer (SCA) + slower ADC  Commercial slower ADC: impractical for space  Commercial slower ADC: analog data handling  No analog processing, ADC on the front-end chip  Front-end integration: 64 channel/chip as a compromise between space and yield (8 FE chips per detector) System partitioning (1)

35. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino  Output lines @ 40MHz clock: two 10bit busses/chip  16 busses per detector: 160 lines ( too many!)  Solution: local digital buffering (2nd chip)  10bit to 8 bit reduction on the digital buffer  Two 8 bit busses per detector (=less material)  Only one 8 bit bus per front-end with acceptable dead time  8 chips on the FE board, 16 chips per detector System partitioning (2)

36. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino A look at the system...

37. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino... and at the chip Preamp Analog memory SAR ADC

38. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Preamplifier specs Input capacitance capacitance: 1 - 3 pF Input signal 1 to 8 mips Peaking time < 50 ns (separation of close tracks) Noise < 500 e- r.m.s Power consumption < 2mW/ch

39. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Preamplifier block diagram (1) PA SH BH In Out Vref

40. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Preamplifier block diagram (2) PA SH BH In Out Vref Vfeed Cf Cz If Rf Rz

41. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Core amplifier schematic In Vcas VB VBC

42. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Baseline holder schematic VB Vref Out In_sh

43. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Buffer schematic VB Vin Vout Cload

44. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Shaper time constant tuning Out SH

45. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Response to 1 mip  V = 164 mV Tp = 32 ns (s)

46. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Layout example PA In Vfeed Cf Cz If Rf Rz

47. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Memory Channel Schematic V ref_w IN + V ref_r OUT Digital Control Logic SW_WSW_RSW_F G. Anelli et al. IEEE TNS, vol48 (3), pp. 435 – 439) June 2001

48. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Which Capacitors for Storage? (1) p+n+ n well p substrate p+n+ p substrate GND V V NMOS Transistor Inversion Region PMOS Transistor without S and D Accumulation Region

49. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Which Capacitors for Storage? (2)

50. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Design of a compact CMOS ADC Conventional SAR based successive approximation scheme Good trade-off between speed, area and power Clock speed: 20 MHz Single rail operation

51. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino ADC design criteria:  Maximum full scale range: Vref  Limit due to noise:  Minimum capacitor allowed by the technology: 75fF  DAC power consumption  Power consumption dominated by the comparator  Vdd, Vin Vref

52. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Capacitive sub-dac without buffer => larger non-linearity, but negligible at 10 bits level DAC Architecture (3)

53. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino DAC layout

54. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Comparator block diagram IN - ++ IN + Vref S1 S2 S3 S4 S5 S6 LATCH

55. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Comparator schematic...

56. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino... and layout

57. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Prototyping  Microelectronics circuits are cheap in large volume  The cost of the masks is a fixed offsed (about 100 k$)  The cost of the wafers is low (about 2k$)  In the research environment the mask costs is usually shared among several users (MPW runs)  Typical prototyping cost: 500 $/mm2

58. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Very first prototypes (RD49) ADCAnalog memory 2 x 2 mm 2, cost 2k$ each

59. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino First SDD front-end prototype 32 channels with preamp and analog memory 16 ADCs on chip Power consumption 5mW/ch Noise: 210 e- @ 3pF External bias and control for test purposes Area: 42mm 2, cost: 21k$

60. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Response to 4fC

61. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Linearity INL < 1%, mainly due to the preamp

62. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Pulse shape fitting Fit to a CR – RC 3

63. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Radiation tolerance y 1 =25.9*x+21 y 2 =26.1*x+34 Noise increase <10%

64. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino From 32 to 64 channels  Final version: 64 channels, same building blocks of the first version plus:  internal bias generators  internal DAC for baseline setting  internal programmable pulse generator  Low drop-out voltage regulators  JTAG protocol for parameters download  LVDS interface.

65. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino The chip …

66. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino …and a test set-up

67. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino A typical problem…

68. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Probe station testing

69. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Probe card detail

70. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino DC parameters  Analog current: average 93.22mA; rms 3.6mA  Digital current: average 131.4mA; rms 5.3mA  Vref1: average 1.926V; rms 4.2mV (design: 1.925V)  Vref0: average 0.524V; rms 2.8mV (design: 0.525V)

71. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Example of signal 1 mip = 108 ADC counts

72. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Example of baseline (1)

73. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Example of baseline (2) Noise : 300 e- rms

74. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Example of calibration (1)

75. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Example of calibration (2)

76. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Example of calibration (3)

77. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Linearity (1)

78. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Linearity (2)

79. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino On chip uniformity  Baseline average 100.8 ADC counts; rms 3.8  Gain: average 108 ADC counts/mip; rms 0.4

80. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino Discrete… 2 cm 1 cm 1 channel minimum power: 10mW power supply: 4V to 25V current: 2.3mA shaping time: 2.4  s noise < 280 e - rms size: 2cm x 1cm

81. University of Siegen – Feb. 20, 2003 Angelo Rivetti – INFN Sezione di Torino … and integrated CMOS 0.25  m technology 64 channels 32 10 bits ADC Power 8mW/ch Shaping time: 40ns Noise < 280 e - rms Size: 1cm x 0.9cm 1 cm Front – end for ALICE SDD