1. Noise Canceling in 1-D Data: Presentation #6 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Feb 23 rd, 2005 Functional Layout/Floorplan Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (28%) –Spice simulation

3. Design Decisions 1.Compared the performance of the mirror adder with the our Mux-Adder Area vs Speed Discovered that they have the same size, so stick to the original one 2. Decided to implement Booth Recoding for the Wallace tree multiplier Need more testing

4. Last Monday…

5. Today…

6. Functional Block Layout ROM Table Input from counter Output to converter

7. Tentative Layout for Fixed Point Multiplier (aka the Wallace) Left Tree Right Tree

8. Pseudo-Layout for the fpAdder

9. Improved Half Adder

10. Improved Full Adder

11. Alternative: Mirror Adder

12. Completed 16 bit 2-1 Mux

13. Challenges… Booth… Revision to Floorplan due to optimized layout of the functional blocks

14. Questions?