1. 1 השעון Hertz=1/sec מחשב פנטיום במהירות של פירושו שהוא מבצע 8^10 *2 מחזורי שעון בשניה. כל מחזור שעון לוקח 200MHZ 5*10^-9=5nanosecond כמה לוקחת פקודה בימינו?

2. 2 Gotta Do Laundry °Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put away ABCD °Dryer takes 30 minutes °“Folder” takes 30 minutes °“Stasher” takes 30 minutes to put clothes into drawers °Washer takes 30 minutes

3. 3 Sequential Laundry Sequential laundry takes 8 hours for 4 loads TaskOrderTaskOrder B C D A 30 Time 30 6 PM 7 8 9 10 11 12 1 2 AM

4. 4 Pipelined Laundry Pipelined laundry takes 3.5 hours for 4 loads! TaskOrderTaskOrder B C D A 12 2 AM 6 PM 7 8 9 10 11 1 Time 30

5. 5 General Definitions Latency: time to completely execute a certain task –for example, time to read a sector from disk is disk access time or disk latency Throughput: amount of work that can be done over a period of time

6. 6 Pipelining Lessons (1/2) Pipelining doesn’t help latency of single task, it helps throughput of entire workload Multiple tasks operating simultaneously using different resources Potential speedup = Number pipe stages Time to “fill” pipeline and time to “drain” it reduces speedup: 2.3X v. 4X in this example 6 PM 789 Time B C D A 30 TaskOrderTaskOrder

7. 7 Pipelining Lessons (2/2) Suppose new Washer takes 20 minutes, new Stasher takes 20 minutes. How much faster is pipeline? Pipeline rate limited by slowest pipeline stage Unbalanced lengths of pipe stages also reduces speedup 6 PM 789 Time B C D A 30 TaskOrderTaskOrder

8. 8 Steps in Executing MIPS 1) IFetch: Fetch Instruction, Increment PC 2) Decode Instruction, Read Registers 3) Execute: Mem-ref:Calculate Address Arith-log: Perform Operation 4) Memory: Load:Read Data from Memory Store:Write Data to Memory 5) Write Back: Write Data to Register

9. 9 Pipelined Execution Representation Every instruction must take same number of steps, also called pipeline “stages”, so some will go idle sometimes IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB IFtchDcdExecMemWB Time

10. 10 Review: Datapath for MIPS Stage 1 Stage 2Stage 3Stage 4Stage 5 Use datapath figure to represent pipeline IFtchDcdExecMemWB ALU I$ Reg D$Reg PC instruction memory +4 rt rs rd registers ALU Data memory imm 1. Instruction Fetch 2. Decode/ Register Read 3. Execute4. Memory 5. Write Back

11. 11 Graphical Pipeline Representation I n s t r. O r d e r Load Add Store Sub Or I$ Time (clock cycles) I$ ALU Reg I$ D$ ALU Reg D$ Reg I$ D$ Reg ALU Reg D$ Reg D$ ALU (In Reg, right half highlight read, left half write) Reg I$

12. 12 Example Suppose 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write Nonpipelined Execution: –lw : IF + Read Reg + ALU + Memory + Write Reg = 2 + 1 + 2 + 2 + 1 = 8 ns –add: IF + Read Reg + ALU + Write Reg = 2 + 1 + 2 + 1 = 6 ns Pipelined Execution: –Max(IF,Read Reg,ALU,Memory,Write Reg) = 2 ns

13. 13 PIPELINE הרעיון מאחורי Never waste time !!!

14. 14 חלוקה לשלבים

15. 15 הוספת הרגיסטרים

16. 16 Instruction memory Address 4 32 0 Add Add result Shift left 2 I n s t r u c t i o n IF/IDEX/MEMMEM/WB M u x 0 1 Add PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data 1 ALU result M u x ALU Zero ID/EX Instruction fetch lw A IF/ID

17. 17 ID/EX

18. 18 EX/MEM

19. 19 Instruction memory Address 4 32 0 Add Add result Shift left 2 I n s t r u c t i o n IF/IDEX/MEM M u x 0 1 Ad d PC 0 Write data M u x 1 Registers Read data 1 Read data 2 Read register 1 Read register 2 16 Sign extend Write register Write data Read data Data memory 1 ALU result M u x ALU Zero ID/EXMEM/WB Memory lw Address MEM/WB

20. 20

21. 21 A correction !!! תיקון Keep the right Rd all the way!

22. 22 So here is the updated CPU;

23. 23 תצוגה גרפית

24. 24 Control

25. 25 קווי הבקרה

26. 26 Datapath with Control

27. 27 דוגמא A demonstration of a sequence of instructions: Lw $10,20($1) Sub $11,$2,$3 And $12,$4,$5 Or $13,$6,$7 Add $14,$8,$9

28. 28

29. 29 ID: and $12, $4, $5

30. 30

31. 31

32. 32 <4> 000 00 0000 000 00 00 0 0 00 0 0 0 1 0 M u x 0 1 Add PC 0 Write data M u x 1 Control Registers Read data 1 Read data 2 Read register 1 Read register 2 Instruction [20–16] Instruction [15–0] Sign extend Instruction [15–11] MemRead M e m W r i t e M u x M u x ALU Read data WB 14 14 Write register Write data Data memory Address Clock 9

33. 33 Pipeline Hazard: Matching socks in later load A depends on D; stall since folder tied up TaskOrderTaskOrder B C D A E F bubble 12 2 AM 6 PM 7 8 9 10 11 1 Time 30

34. 34 Problems for Computers Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle –Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) –Control hazards: Pipelining of branches & other instructions stall the pipeline until the hazard “bubbles” in the pipeline –Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)

35. 35 An example for data hazards: sub$2, $1, $3 and $12, $2, $5 or$13, $6, $2 add$14, $2, $2 sw$15, 100($2)

36. 36 An example for data hazards: sub$2, $1, $3 and $12, $2, $5 or$13, $6, $2 add$14, $2, $2 sw$15, 100($2) An example for data hazards: Register $2 is updated only at the WB phase, i.e., the 5th clock cycle (actually at the end of the 5th clock cycle). However, we try to use it at the 3rd clock cycle when we read $2 at the decode phase of the and instruction

37. 37 Graphic representation of data hazards:

38. 38 sub$2, $1, $3 nop and $12, $2, $5 or$13, $6, $2 add$14, $2, $2 sw$15, 100($2) Solving data hazards by adding nops

39. 39 Solving data hazards by adding nops Program execution order (in instructions) and $12, $2, $ or $13, $6, $2 add $14, $2, $ sw $15, 100($2 5 2 ) g IMReg IM Reg DMReg IMDMReg IMDMRe Reg Reg Reg DM IMRegDM R e g IMRegDM Reg IMRegDM R e g IMRegDM R e g sub $2, $1, $3 nop

40. 40 Graphic representation of data hazards:

41. 41 Forwarding – גניבת הערכים

42. 42 Forwarding (done at the execute phase) If ID/EX.Rs=EX/MEM.Rd, i.e., the Rd of the previous instruction equals the Rs of the current instruction (which is in the “decode” phase), then we use the “ALUout” of the previous instruction instead of the output of the GPR. If ID/EX.Rs=MEM/WB.Rd, i.e., the Rd of the previous instruction equals the Rs of the current instruction (which is in the “decode” phase), then we use the “ALUout” of the previous instruction instead of the output of the GPR. [ similarly, compare also ID/EX.Rt to MEM/WB.Rd ] Similarly, compare also ID/EX.Rt to EX/MEM.Rd and to MEM/WB.Rd

43. 43 Data hazard from previous instruction: ALU Src A: If (ID/EX.Rs = = EX/MEM.Rd) use the “ ALUOut ” instead of Rs I.e., if Rs of the current executing instruction = = Rd of the previous instruction The actual equations are: if ((EX/MEM.RegWrite = = ‘ 1 ” )&& (EX/MEM.Rd <> 0)&& (ID/EX.Rs = = EX/MEM.Rd)) => ForwardA= “ 1,0 ” ALU Src B: If (ID/EX.Rt = = EX/MEM.Rd) use the “ ALUOut ” instead of Rt I.e., if Rt of the current executing instruction = = Rd of the previous instruction The actual equations are: if ((EX/MEM.RegWrite = = ‘ 1 ” )&& (EX/MEM.Rd <> 0)&& (ID/EX.Rt = = EX/MEM.Rd)) => ForwardB= “ 1,0 ”

44. 44 Data hazard from 2 instructions back: ALU Src A: If (ID/EX.Rs = = MEM/WB.Rd) use the GPR “ write data ” instead of Rs I.e., if Rs of the current executing instruction = = Rd of 2 instructions ago The actual equations are: if ((MEM/WB.RegWrite = = ‘ 1 ” )&& (MEM/WB.Rd <> 0)&& (ID/EX.Rs = = MEM/WB.Rd)) => ForwardA= “ 0,1 ” ALU Src B: If (ID/EX.Rt = = MEM/WB.Rd) use the GPR “ write data ” instead of Rt I.e., if Rt of the current executing instruction = = Rd of 2 instructions ago The actual equations are: if ((MEM/WB.RegWrite = = ‘ 1 ” )&& (MEM/WB.Rd <> 0)&& (ID/EX.Rt = = MEM/WB.Rd)) => ForwardB= “ 0,1 ” Double hazard: If there is a hazard from previous inst and the instruction before that?We should chhose the data from the previous instruction, it is up to date ( “ newer ” )!

45. 45 An example for forwarding דוגמא Sub $2, $1, $3 And $4, $2, $5 needs forwarding from the previous instruction Or$4, $4, $2 needs forwarding from two instructions back Add $9, $4, $2 needs forwarding from 3 instructions back (thru the “ transparent ” GPR) Here we discuss the $2 register only (The first two cases are handled in the execute phase, the last one, in the decode phase).

46. 46 An example for forwarding דוגמא Sub $2, $1, $3 And $4, $2, $5 Or$4, $4, $2 needs forwarding from the previous instruction Add $9, $4, $2 needs forwarding from the previous instruction Here we discuss the $4 register and there are two case (the 2nd one in purple)

47. 47 Since Rs=2 and Rd of previous inst. was 2, we use ALUout instead of Rs

48. 48 In red we see forwarding from two instructions back (Mem->Exec.), in purple, from previous instruction (WB->Exec.), in blue, from 3 instructions back (WB- >Decode).

49. 49 The solution does not work for lw - לא תמיד הפתרון עובד (in lw we do not have the data in the pipe!, it comes from the data memory!) If the previous instruction was lw to a register and we try to use the register in the current instruction, we have a problem, since we cannot go back in time! One solution is to avoid such cases by adding a nop (by the Assembler) whenever Rt of the lw is equal to Rs or Rt of the following instruction.

50. 50 Another h/w solution is to add Bubbles, i.e., add nop by hardware “nop” We need to hold IF/ID for one ck cycle and insert a “ nop: into ID/EX. This is equal to adding a nop instruction by the Assembler.

51. 51 Hazard detection unit We need to hold the IF/ID and PC for one ck cycle and insert a “ nop: into ID/EX. This is equal to adding a nop instruction by the Assembler. If (ID/EX.MemRd)&& ( (ID/EX.Rt= =IF/ID.Rs) || (ID/EX.Rt= =IF/ID.Rt) ) we must “ stall ” the pipeline! This means that prev. inst was lw and it was to the current Rs or Rt. (of course if one of them is not used, don ’ t stall) Holding means ” freeze ” the IF/ID and the PC for 1 clock cycle Hold the IF/ID by not giving a IF/IDWrire signal and do not increment the PC (which already points at the nex instruction) by not giving the PCWrite signal. Inserting a nop is by clearing all control signals. Rt from prev. inst. Rs, Rt of current inst. identifies lw

52. 52 An example for lw hazard detection דוגמא lw $2, 20($1) And $4, $2, $5 Or$4, $4, $2 Add $9, $4, $2

53. 53

54. 54 The lw instruction is in the WB phase. $2 is “ being written ”. We can use $2 in the Execute phase of the and instruction, with the help of forwarding.

55. 55

56. 56 Just to remind us how branch is handled we show again the Datapath with Control

57. 57 Branch Hazards Here we calc.Rs-Rt Here we decide to branch (switching the address to the PC and issuing PCWrite Cond) These 3 instructions should be “killed” before they do harm, I.e., change any register. In cc5 we already use the new PC calculated by the branch. (PC=72)

58. 58 The situation was better if we some how “moved” the branch address calculation one ck earlier. This is easy to dosince sign extension and shift are only wires. We just need to move the branch address ALU 1 register to the left. Rverything happens 1 ck earlier and so we’ll have to “kill” only two instructions. Next, we’ll add a fast comparator which will compare Rs and Rt at the same ck cycle of the “decode” phase. (Instead of using the ALU to calc. Rs-Rt, we’ll built a simple and fast xor circuit). This means extra h/w but now we earned one more ck cycle. So, we have to kill only a single instruction. Killing an instruction also called “flushing” the pipeline, is easily done by clraing the IF/ID register of the instruction following the branch (if the branch is successful)

59. 59 Flushing

60. 60 An example for flushing דוגמא sub$10, $4, $8 beq $1, $3, 7 and$12, $2, $5 lw $4, 50($7)

61. 61 sub$10, $4, $8 beq $1, $3, 7 and$12, $2, $5 lw $4, 50($7)

62. 62 Summary of hazards Data hazards: * Forward from previous instruction * Forward from two instructions ago * (Forward thru “ transparent ” GPR = from 3 instructions ago) * If we cannot forward, (after lw) we stall the pipe by inserting a nop and freezing IF/ID and PC for 1 ck cycle Control hazards: * If branch is successful we flush the instruction following the branch (which is at the IF/ID register. We just clear the register) Notes: In the real MIPS CPU, no flush was employed. This give the compiler the opportunity to put useful instructions following the branch. This explains why the simulator always performs the instruction following the branch.this is called a delayed branch. Also, in the real MIPS CPU no lw stall was used. Again this give some freedom to the compiler to choose whether to put a nop following lw or some useful instruction. This is called a delayed load.