1. Lecture 24: Interconnect parasitics
EECS 312
Reading: 8.2.1, (text), 4.2, (2nd edition)
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2. Last Time 1T DRAM operation
A major component of digital systems today
Great density, relies on charge sharing to read data, must be refreshed periodically (leakage currents)
Packaging provides an interface from the chip to the external world
To send signals off-chip, we need to drive large capacitances
This is best done by creating a cascaded buffer chain where each inverter is ~3X larger than its driver
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3. Lecture Overview Simultaneous switching noise (L*di/dt noise)
Introduce wiring capacitance
Models to calculate these parameters
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4. L di/dt
Significant inductance due to packaging between the actual power supply and the gates themselves
Large current draws across this L  voltage drop
Often called simultaneous switching noise (SSN) since a lot of simultaneous switching will increase di/dt
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5. SSN Analysis
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6. Voltage waveforms due to SSN
Ground bounce shown at left (GND > 0V)
How to limit:
1) Use packaging with small inductance
2) Slow down transitions at I/O pads (reduce di/dt)
3) Low-swing I/O – incompatible with external chips (usually I/O voltage > regular voltage) 8
Voltage 4
1 active driver 0V
time
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7. IC Wiring (Interconnect)
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8. Impact of Interconnect Parasitics
Not covered in 312
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9. Nature of Interconnect
Remember scaling?
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10. Real Data on nature of interconnect
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11. Capacitance: The Parallel Plate Model
ILD: Interlevel dielectric L W T
Bottom plate of cap can be another metal layer H
SiO
ILD 2
Substrate
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12. Permittivities of modern insulators
There is a tremendous push towards low-k (er < 4.0) dielectrics for metallization
This helps delay and power!
Difficult to manufacture
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13. Fringing Capacitance w Twire S
H is sometimes called T – can be confusing
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14. Typical Wiring Capacitance Values
Shaded: fringe Unshaded: area
in [aF/mm] 1000aF = 1fF
Bottom plate
Top plate
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15. Capacitance values for diff. configs
Parallel plate model significantly underestimates capacitance when width is comparable to ILD height
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16. Interwire (Coupling) Capacitance
Leads to coupling effects among adjacent wires
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17. Interwire Capacitance
Layer
Poly M1 M2 M3 M4 M5
Capacitance (aF/mm), min spacing 40 95 85
115
Example: if two wires on layer Metal 3 run parallel to each other for 1mm, the capacitance between these two wires is 85aF/mm * 1000mm = 85000aF = 85fF
In today’s process technologies, interwire capacitance can account for up to 80% of the total wire capacitance M1
Sub
M1 Sub
Past
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Present / Future

18. Empirical Capacitance Models
Empirical capacitance models are the easiest and fastest way to find accurate capacitances for interconnect configurations
Limited configurations can be investigated, 3D effects are not considered
Capacitance per unit length
This model assumes no neighboring wires; optimistic
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19. Wire Capacitance Rule of Thumb
Modern processes have per unit length wiring capacitances around 2 pF/cm
Equal to 0.2 fF per micron of wirelength
This is fairly accurate for wire widths < 2mm
Compare this to the amount of MOSFET gate capacitance ~ 1 fF / micron width
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20. Example Back-end process
Intel
6 metal layers
0.13mm process
Vias shown (connect layers)
Aspect ratio = Twire/Wmin
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21. Lecture Summary
Simultaneous switching noise is a key problem for off-chip drivers
Drive them as slowly as allowed
General interconnect characteristics
Local wires and global wires
Many metal levels, connect with vias
Capacitance is the primary parasitic
Area, fringing, interwire components
Interwire dominates today
Both simple and complex models exist to compute capacitance as a function of wire geometry
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22. Inductance
Inductance, L, is the measure of ability to store energy in the form of a magnetic field
Inductance of a wire consists of a self-inductance and a mutual inductance term
Z = R + jwL
At high frequencies, inductance can become an appreciable portion of the total impedance
Angular frequency = 2pf
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24. Inductance is a weak function of conductor dimensions
Most strongly influenced by distance to return path – commonly the power grid
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26. Why is inductance important?
Inductance may lead to:
Voltage overshoot
Ringing / non-monotonic voltage response
Faster rise/fall times (enhancing noise)
Higher performance leads to higher inductive effects
Bandwith ~ 0.35 / rise time
If L * Bandwidth becomes comparable to R, inductive effects need to be considered
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28. Inductive effects in action
- Yellow lines are distributed RLC simulation results of a 5 mm line with 30 ps input rise time to large CMOS inverter
- Overshoot and non-monotonic response is seen
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29. Inductance Trends
Inductance is a weak function of conductor dimensions (logarithmic)
Inductance is a strong function of current return path distance
Want to have a nearby ground line to provide a small current loop
Inductance is most significant in long, fast-switching nets with low resistance
Clocks are the most susceptible
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30. Dealing with Inductance
DEC approach in Alpha use entire planes of metal as references (Vdd and GND) to eliminate inductance
- Loss of routing density, added metal layers reduce yield & raise costs
Another industry approach uses shield wires every ~ 3 signal lines in a dense array
Vdd
GND
Bus lines
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31. How to model inductance?
Efficient RLC modeling is possible now
- Asymptotic Waveform Evaluation (AWE)
Inductance extraction is not available now
- Hot research topic; should not be solved in the next few years - Difficult due to uncertainty in current return path
Figures of merit can be used; Inductance important when: C R L
- Line must be long for the time-of-flight to be comparable to rise time - Line must be short enough such that attenuation does not eliminate inductive effects
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32. The Transmission Line
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33. Lossless Transmission Line - Parameters
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34. Wave Propagation Speed
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35. Wave Reflection for Different Terminations
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36. Transmission Line Response (RL= )
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37. Lattice Diagram
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38. When to Consider Transmission Line Effects?
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