1. CS252/Kubiatowicz Lec 23.1 11/17/99 CS252 Graduate Computer Architecture Lecture 23 I/O Continued November 17, 1999 Prof. John Kubiatowicz

2. CS252/Kubiatowicz Lec 23.2 11/17/99 Review: Disk Device Terminology Disk Latency = Queuing Time + Seek Time + Rotation Time + Xfer Time + Ctrl Time Order of magnitude times for 4K byte transfers: Seek: 12 ms or less Rotate: 4.2 ms @ 7200 rpm = 0.5 rev/(7200 rpm/60m/s) (8.3 ms @ 3600 rpm ) Xfer: 1 ms @ 7200 rpm (2 ms @ 3600 rpm) Ctrl: 2 ms (big variation) Disk Latency = Queuing Time + (12 + 4.2 + 1 + 2)ms = QT + 19.2ms Average Service Time = 19.2 ms

3. CS252/Kubiatowicz Lec 23.3 11/17/99 But: What about queue time? Or: why nonlinear response Response time = Queue + Device Service time 100% Response Time (ms) Throughput (% total BW) 0 100 200 300 0% Proc Queue IOCDevice Metrics: Response Time Throughput

4. CS252/Kubiatowicz Lec 23.4 11/17/99 Departure to discuss queueing theory (On board)

5. CS252/Kubiatowicz Lec 23.5 11/17/99 Introduction to Queueing Theory More interested in long term, steady state than in startup => Arrivals = Departures Little’s Law: Mean number tasks in system = arrival rate x mean reponse time –Observed by many, Little was first to prove Applies to any system in equilibrium, as long as nothing in black box is creating or destroying tasks ArrivalsDepartures

6. CS252/Kubiatowicz Lec 23.6 11/17/99 A Little Queuing Theory: Notation Queuing models assume state of equilibrium: input rate = output rate Notation: r average number of arriving customers/second T ser average time to service a customer (tradtionally µ = 1/ T ser ) userver utilization (0..1): u = r x T ser (or u = r / T ser ) T q average time/customer in queue T sys average time/customer in system: T sys = T q + T ser L q average length of queue: L q = r x T q L sys average length of system: L sys = r x T sys Little’s Law: Length system = rate x Time system (Mean number customers = arrival rate x mean service time) ProcIOCDevice Queue server System

7. CS252/Kubiatowicz Lec 23.7 11/17/99 A Little Queuing Theory Service time completions vs. waiting time for a busy server: randomly arriving event joins a queue of arbitrary length when server is busy, otherwise serviced immediately –Unlimited length queues key simplification A single server queue: combination of a servicing facility that accomodates 1 customer at a time (server) + waiting area (queue): together called a system Server spends a variable amount of time with customers; how do you characterize variability? –Distribution of a random variable: histogram? curve? ProcIOCDevice Queue server System

8. CS252/Kubiatowicz Lec 23.8 11/17/99 A Little Queuing Theory Server spends a variable amount of time with customers –Weighted mean m1 = (f1 x T1 + f2 x T2 +...+ fn x Tn)/F (F=f1 + f2...) –variance = (f1 x T1 2 + f2 x T2 2 +...+ fn x Tn 2 )/F – m1 2 »Must keep track of unit of measure (100 ms 2 vs. 0.1 s 2 ) –Squared coefficient of variance: C = variance/m1 2 »Unitless measure (100 ms 2 vs. 0.1 s 2 ) Exponential distribution C = 1 : most short relative to average, few others long; 90% < 2.3 x average, 63% < average Hypoexponential distribution C 90% < 2.0 x average, only 57% < average Hyperexponential distribution C > 1 : further from average C=2.0 => 90% < 2.8 x average, 69% < average ProcIOCDevice Queue server System Avg.

9. CS252/Kubiatowicz Lec 23.9 11/17/99 A Little Queuing Theory: Variable Service Time Server spends a variable amount of time with customers –Weighted mean m1 = (f1xT1 + f2xT2 +...+ fnXTn)/F (F=f1+f2+...) –Squared coefficient of variance C Disk response times C ­ 1.5 (majority seeks < average) Yet usually pick C = 1.0 for simplicity Another useful value is average time must wait for server to complete task: m1(z) –Not just 1/2 x m1 because doesn’t capture variance –Can derive m1(z) = 1/2 x m1 x (1 + C) –No variance => C= 0 => m1(z) = 1/2 x m1 ProcIOCDevice Queue server System

10. CS252/Kubiatowicz Lec 23.10 11/17/99 A Little Queuing Theory: Average Wait Time Calculating average wait time in queue T q –If something at server, it takes to complete on average m1(z) –Chance server is busy = u; average delay is u x m1(z) –All customers in line must complete; each avg T s er T q = u x m1(z) + L q x T s er = 1/2 x u x T ser x (1 + C) + L q x T s er T q = 1/2 x u x T s er x (1 + C) + r x T q x T s er T q = 1/2 x u x T s er x (1 + C) + u x T q T q x (1 – u) = T s er x u x (1 + C) /2 T q = T s er x u x (1 + C) / (2 x (1 – u)) Notation: raverage number of arriving customers/second T ser average time to service a customer userver utilization (0..1): u = r x T ser T q average time/customer in queue L q average length of queue:L q = r x T q

11. CS252/Kubiatowicz Lec 23.11 11/17/99 A Little Queuing Theory: M/G/1 and M/M/1 Assumptions so far: –System in equilibrium –Time between two successive arrivals in line are random –Server can start on next customer immediately after prior finishes –No limit to the queue: works First-In-First-Out –Afterward, all customers in line must complete; each avg T ser Described “memoryless” or Markovian request arrival (M for C=1 exponentially random), General service distribution (no restrictions), 1 server: M/G/1 queue When Service times have C = 1, M/M/1 queue T q = T ser x u x (1 + C) /(2 x (1 – u)) = T ser x u / (1 – u) T ser average time to service a customer userver utilization (0..1): u = r x T ser T q average time/customer in queue

12. CS252/Kubiatowicz Lec 23.12 11/17/99 A Little Queuing Theory: An Example processor sends 10 x 8KB disk I/Os per second, requests & service exponentially distrib., avg. disk service = 20 ms On average, how utilized is the disk? –What is the number of requests in the queue? –What is the average time spent in the queue? –What is the average response time for a disk request? Notation: raverage number of arriving customers/second = 10 T ser average time to service a customer = 20 ms (0.02s) userver utilization (0..1): u = r x T ser = 10/s x.02s = 0.2 T q average time/customer in queue = T ser x u / (1 – u) = 20 x 0.2/(1-0.2) = 20 x 0.25 = 5 ms (0.005s) T sys average time/customer in system: T sys =T q +T ser = 25 ms L q average length of queue:L q = r x T q = 10/s x.005s = 0.05 requests in queue L sys average # tasks in system: L sys = r x T sys = 10/s x.025s = 0.25

13. CS252/Kubiatowicz Lec 23.13 11/17/99 A Little Queuing Theory: Another Example processor sends 20 x 8KB disk I/Os per sec, requests & service exponentially distrib., avg. disk service = 12 ms On average, how utilized is the disk? –What is the number of requests in the queue? –What is the average time a spent in the queue? –What is the average response time for a disk request? Notation: raverage number of arriving customers/second= 20 T ser average time to service a customer= 12 ms userver utilization (0..1): u = r x T ser = 20/s x.012s = 0.24 T q average time/customer in queue = T s er x u / (1 – u) = 12 x 0.24/(1-0.24) = 12 x 0.32 = 3.8 ms T sys average time/customer in system: T sys =T q +T ser = 15.8 ms L q average length of queue:L q = r x T q = 20/s x.0038s = 0.076 requests in queue L sys average # tasks in system : L sys = r x T sys = 20/s x.016s = 0.32

14. CS252/Kubiatowicz Lec 23.14 11/17/99 A Little Queuing Theory: Yet Another Example Suppose processor sends 10 x 8KB disk I/Os per second, squared coef. var.(C) = 1.5, avg. disk service time = 20 ms On average, how utilized is the disk? –What is the number of requests in the queue? –What is the average time a spent in the queue? –What is the average response time for a disk request? Notation: raverage number of arriving customers/second= 10 T ser average time to service a customer= 20 ms userver utilization (0..1): u = r x T ser = 10/s x.02s = 0.2 T q average time/customer in queue = T ser x u x (1 + C) /(2 x (1 – u)) = 20 x 0.2(2.5)/2(1 – 0.2) = 20 x 0.32 = 6.25 ms T sys average time/customer in system: T sys = T q +T ser = 26 ms L q average length of queue:L q = r x T q = 10/s x.006s = 0.06 requests in queue L sys average # tasks in system :L sys = r x T sys = 10/s x.026s = 0.26

15. CS252/Kubiatowicz Lec 23.15 11/17/99 Manufacturing Advantages of Disk Arrays 14” 10”5.25”3.5” Disk Array: 1 disk design Conventional: 4 disk designs Low End High End Disk Product Families

16. CS252/Kubiatowicz Lec 23.16 11/17/99 Replace Small # of Large Disks with Large # of Small Disks! (1988 Disks) Data Capacity Volume Power Data Rate I/O Rate MTTF Cost IBM 3390 (K) 20 GBytes 97 cu. ft. 3 KW 15 MB/s 600 I/Os/s 250 KHrs $250K IBM 3.5" 0061 320 MBytes 0.1 cu. ft. 11 W 1.5 MB/s 55 I/Os/s 50 KHrs $2K x70 23 GBytes 11 cu. ft. 1 KW 120 MB/s 3900 IOs/s ??? Hrs $150K Disk Arrays have potential for large data and I/O rates high MB per cu. ft., high MB per KW reliability?

17. CS252/Kubiatowicz Lec 23.17 11/17/99 Array Reliability Reliability of N disks = Reliability of 1 Disk ÷ N 50,000 Hours ÷ 70 disks = 700 hours Disk system MTTF: Drops from 6 years to 1 month! Arrays (without redundancy) too unreliable to be useful! Hot spares support reconstruction in parallel with access: very high media availability can be achieved Hot spares support reconstruction in parallel with access: very high media availability can be achieved

18. CS252/Kubiatowicz Lec 23.18 11/17/99 Redundant Arrays of Disks Files are "striped" across multiple spindles Redundancy yields high data availability Disks will fail Contents reconstructed from data redundantly stored in the array Capacity penalty to store it Bandwidth penalty to update Mirroring/Shadowing (high capacity cost) Horizontal Hamming Codes (overkill) Parity & Reed-Solomon Codes Failure Prediction (no capacity overhead!) VaxSimPlus — Technique is controversial Techniques:

19. CS252/Kubiatowicz Lec 23.19 11/17/99 Redundant Arrays of Disks RAID 1: Disk Mirroring/Shadowing Each disk is fully duplicated onto its "shadow" Very high availability can be achieved Bandwidth sacrifice on write: Logical write = two physical writes Reads may be optimized Most expensive solution: 100% capacity overhead Targeted for high I/O rate, high availability environments recovery group

20. CS252/Kubiatowicz Lec 23.20 11/17/99 Redundant Arrays of Disks RAID 3: Parity Disk P 10010011 11001101 10010011... logical record 1001001110010011 1100110111001101 1001001110010011 0011000000110000 Striped physical records Parity computed across recovery group to protect against hard disk failures 33% capacity cost for parity in this configuration wider arrays reduce capacity costs, decrease expected availability, increase reconstruction time Arms logically synchronized, spindles rotationally synchronized logically a single high capacity, high transfer rate disk Targeted for high bandwidth applications: Scientific, Image Processing

21. CS252/Kubiatowicz Lec 23.21 11/17/99 Redundant Arrays of Disks RAID 5+: High I/O Rate Parity A logical write becomes four physical I/Os Independent writes possible because of interleaved parity Reed-Solomon Codes ("Q") for protection during reconstruction A logical write becomes four physical I/Os Independent writes possible because of interleaved parity Reed-Solomon Codes ("Q") for protection during reconstruction D0D1D2 D3 P D4D5D6 P D7 D8D9P D10 D11 D12PD13 D14 D15 PD16D17 D18 D19 D20D21D22 D23 P.............................. Disk Columns Increasing Logical Disk Addresses Stripe Unit Targeted for mixed applications

22. CS252/Kubiatowicz Lec 23.22 11/17/99 Problems of Disk Arrays: Small Writes D0D1D2 D3 P D0' + + D1D2 D3 P' new data old data old parity XOR (1. Read) (2. Read) (3. Write) (4. Write) RAID-5: Small Write Algorithm 1 Logical Write = 2 Physical Reads + 2 Physical Writes

23. CS252/Kubiatowicz Lec 23.23 11/17/99 Subsystem Organization host array controller single board disk controller single board disk controller single board disk controller single board disk controller host adapter manages interface to host, DMA control, buffering, parity logic physical device control often piggy-backed in small format devices striping software off-loaded from host to array controller no applications modifications no reduction of host performance

24. CS252/Kubiatowicz Lec 23.24 11/17/99 System Availability: Orthogonal RAIDs Array Controller String Controller String Controller String Controller String Controller String Controller String Controller... Data Recovery Group: unit of data redundancy Redundant Support Components: fans, power supplies, controller, cables End to End Data Integrity: internal parity protected data paths

25. CS252/Kubiatowicz Lec 23.25 11/17/99 System-Level Availability Fully dual redundant I/O Controller Array Controller......... Recovery Group Goal: No Single Points of Failure Goal: No Single Points of Failure host with duplicated paths, higher performance can be obtained when there are no failures

26. CS252/Kubiatowicz Lec 23.26 11/17/99 Review: Storage System Issues Historical Context of Storage I/O Secondary and Tertiary Storage Devices Storage I/O Performance Measures Processor Interface Issues A Little Queuing Theory Redundant Arrarys of Inexpensive Disks (RAID) I/O Buses ABCs of UNIX File Systems I/O Benchmarks Comparing UNIX File System Performance

27. CS252/Kubiatowicz Lec 23.27 11/17/99 CS 252 Administrivia Upcoming schedule of project events in CS 252 –Friday Nov 12: finish I/O? Start multiprocessing/networking –Remaining 3 lectures before Thanksgiving: multiprocessing –Wednesday Dec 1: Midterm I –Friday Dec 3: Esoteric computation. »Quantum/DNA/Nano computing –Next week: Midproject meetings. Tuesday? (Sharad?) –Tue/Wed Dec 7/8 for oral reports? –Friday Dec 10: project reports due. Get moving!!!

28. CS252/Kubiatowicz Lec 23.28 11/17/99 A Bus Is: shared communication link single set of wires used to connect multiple subsystems A Bus is also a fundamental tool for composing large, complex systems –systematic means of abstraction Control Datapath Memory Processor Input Output What is a bus?

29. CS252/Kubiatowicz Lec 23.29 11/17/99 Buses

30. CS252/Kubiatowicz Lec 23.30 11/17/99 Versatility: –New devices can be added easily –Peripherals can be moved between computer systems that use the same bus standard Low Cost: –A single set of wires is shared in multiple ways Memory Processer I/O Device Advantages of Buses

31. CS252/Kubiatowicz Lec 23.31 11/17/99 It creates a communication bottleneck –The bandwidth of that bus can limit the maximum I/O throughput The maximum bus speed is largely limited by: –The length of the bus –The number of devices on the bus –The need to support a range of devices with: »Widely varying latencies »Widely varying data transfer rates Memory Processer I/O Device Disadvantage of Buses

32. CS252/Kubiatowicz Lec 23.32 11/17/99 Control lines: –Signal requests and acknowledgments –Indicate what type of information is on the data lines Data lines carry information between the source and the destination: –Data and Addresses –Complex commands Data Lines Control Lines General Organization of a Bus

33. CS252/Kubiatowicz Lec 23.33 11/17/99 A bus transaction includes two parts: –Issuing the command (and address) – request –Transferring the data – action Master is the one who starts the bus transaction by: –issuing the command (and address) Slave is the one who responds to the address by: –Sending data to the master if the master ask for data –Receiving data from the master if the master wants to send data Bus Master Bus Slave Master issues command Data can go either way Master versus Slave

34. CS252/Kubiatowicz Lec 23.34 11/17/99 DMA (Direct Memory Access)? Typical I/O devices must transfer large amounts of data to memory of processor: –Disk must transfer complete block (4K? 16K?) –Large packets from network –Regions of frame buffer DMA gives external device ability to write memory directly: much lower overhead than having processor request one word at a time. –Processor (or at least memory system) acts like slave Issue: Cache coherence: –What if I/O devices write data that is currently in processor Cache? »The processor may never see new data! –Solutions: »Flush cache on every I/O operation (expensive) »Have hardware invalidate cache lines (remember “Coherence” cache misses?)

35. CS252/Kubiatowicz Lec 23.35 11/17/99 Types of Buses Processor-Memory Bus (design specific) –Short and high speed –Only need to match the memory system »Maximize memory-to-processor bandwidth –Connects directly to the processor –Optimized for cache block transfers I/O Bus (industry standard) –Usually is lengthy and slower –Need to match a wide range of I/O devices –Connects to the processor-memory bus or backplane bus Backplane Bus (standard or proprietary) –Backplane: an interconnection structure within the chassis –Allow processors, memory, and I/O devices to coexist –Cost advantage: one bus for all components

36. CS252/Kubiatowicz Lec 23.36 11/17/99 Processor/Memory Bus PCI Bus I/O Busses Example: Pentium System Organization

37. CS252/Kubiatowicz Lec 23.37 11/17/99 A Computer System with One Bus: Backplane Bus A single bus (the backplane bus) is used for: –Processor to memory communication –Communication between I/O devices and memory Advantages: Simple and low cost Disadvantages: slow and the bus can become a major bottleneck Example: IBM PC - AT ProcessorMemory I/O Devices Backplane Bus

38. CS252/Kubiatowicz Lec 23.38 11/17/99 A Two-Bus System I/O buses tap into the processor-memory bus via bus adaptors: –Processor-memory bus: mainly for processor-memory traffic –I/O buses: provide expansion slots for I/O devices Apple Macintosh-II –NuBus: Processor, memory, and a few selected I/O devices –SCCI Bus: the rest of the I/O devices ProcessorMemory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus

39. CS252/Kubiatowicz Lec 23.39 11/17/99 A Three-Bus System A small number of backplane buses tap into the processor-memory bus –Processor-memory bus is only used for processor-memory traffic –I/O buses are connected to the backplane bus Advantage: loading on the processor bus is greatly reduced ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus

40. CS252/Kubiatowicz Lec 23.40 11/17/99 North/South Bridge architectures: separate buses Separate sets of pins for different functions –Memory bus –Caches –Graphics bus (for fast frame buffer) –I/O buses are connected to the backplane bus Advantage: –Buses can run at different speeds –Much less overall loading! ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus “backside cache”

41. CS252/Kubiatowicz Lec 23.41 11/17/99 Bunch of Wires Physical / Mechanical Characterisics – the connectors Electrical Specification Timing and Signaling Specification Transaction Protocol What defines a bus?

42. CS252/Kubiatowicz Lec 23.42 11/17/99 Synchronous Bus: –Includes a clock in the control lines –A fixed protocol for communication that is relative to the clock –Advantage: involves very little logic and can run very fast –Disadvantages: »Every device on the bus must run at the same clock rate »To avoid clock skew, they cannot be long if they are fast Asynchronous Bus: –It is not clocked –It can accommodate a wide range of devices –It can be lengthened without worrying about clock skew –It requires a handshaking protocol Synchronous and Asynchronous Bus

43. CS252/Kubiatowicz Lec 23.43 11/17/99 ° ° ° MasterSlave Control Lines Address Lines Data Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Busses so far

44. CS252/Kubiatowicz Lec 23.44 11/17/99 Bus Transaction Arbitration: Who gets the bus Request: What do we want to do Action: What happens in response

45. CS252/Kubiatowicz Lec 23.45 11/17/99 One of the most important issues in bus design: –How is the bus reserved by a device that wishes to use it? Chaos is avoided by a master-slave arrangement: –Only the bus master can control access to the bus: It initiates and controls all bus requests –A slave responds to read and write requests The simplest system: –Processor is the only bus master –All bus requests must be controlled by the processor –Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way Arbitration: Obtaining Access to the Bus

46. CS252/Kubiatowicz Lec 23.46 11/17/99 Multiple Potential Bus Masters: the Need for Arbitration Bus arbitration scheme: –A bus master wanting to use the bus asserts the bus request –A bus master cannot use the bus until its request is granted –A bus master must signal to the arbiter after finish using the bus Bus arbitration schemes usually try to balance two factors: –Bus priority: the highest priority device should be serviced first –Fairness: Even the lowest priority device should never be completely locked out from the bus Bus arbitration schemes can be divided into four broad classes: –Daisy chain arbitration –Centralized, parallel arbitration –Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. –Distributed arbitration by collision detection: Each device just “goes for it”. Problems found after the fact.

47. CS252/Kubiatowicz Lec 23.47 11/17/99 The Daisy Chain Bus Arbitrations Scheme Advantage: simple Disadvantages: –Cannot assure fairness: A low-priority device may be locked out indefinitely –The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Grant Release Request wired-OR

48. CS252/Kubiatowicz Lec 23.48 11/17/99 Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req Centralized Parallel Arbitration

49. CS252/Kubiatowicz Lec 23.49 11/17/99 All agents operate synchronously All can source / sink data at same rate => simple protocol –just manage the source and target Simplest bus paradigm

50. CS252/Kubiatowicz Lec 23.50 11/17/99 Even memory busses are more complex than this –memory (slave) may take time to respond –it may need to control data rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Simple Synchronous Protocol

51. CS252/Kubiatowicz Lec 23.51 11/17/99 Slave indicates when it is prepared for data xfer Actual transfer goes at bus rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Data1 Wait Typical Synchronous Protocol

52. CS252/Kubiatowicz Lec 23.52 11/17/99 Separate versus multiplexed address and data lines: –Address and data can be transmitted in one bus cycle if separate address and data lines are available –Cost: (a) more bus lines, (b) increased complexity Data bus width: –By increasing the width of the data bus, transfers of multiple words require fewer bus cycles –Example: SPARCstation 20’s memory bus is 128 bit wide –Cost: more bus lines Block transfers: –Allow the bus to transfer multiple words in back-to-back bus cycles –Only one address needs to be sent at the beginning –The bus is not released until the last word is transferred –Cost: (a) increased complexity (b) decreased response time for request Increasing the Bus Bandwidth

53. CS252/Kubiatowicz Lec 23.53 11/17/99 Overlapped arbitration –perform arbitration for next transaction during current transaction Bus parking –master can holds onto bus and performs multiple transactions as long as no other master makes request Overlapped address / data phases (prev. slide) –requires one of the above techniques Split-phase (or packet switched) bus –completely separate address and data phases –arbitrate separately for each –address phase yield a tag which is matched with data phase ”All of the above” in most modern memory buses Increasing Transaction Rate on Multimaster Bus

54. CS252/Kubiatowicz Lec 23.54 11/17/99 BusMBusSummitChallengeXDBus OriginatorSunHPSGISun Clock Rate (MHz)40604866 Address lines364840muxed Data lines64128256144 (parity) Data Sizes (bits)2565121024512 Clocks/transfer454? Peak (MB/s)320(80)96012001056 MasterMultiMultiMultiMulti ArbitrationCentralCentralCentralCentral Slots16910 Busses/system1112 Length13 inches12? inches17 inches 1993 MP Server Memory Bus Survey: GTL revolution

55. CS252/Kubiatowicz Lec 23.55 11/17/99 Address Data Read Req Ack Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack Asynchronous Handshake

56. CS252/Kubiatowicz Lec 23.56 11/17/99 Address Data Read Req Ack Master Asserts AddressNext Address t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack Read Transaction Slave Data

57. CS252/Kubiatowicz Lec 23.57 11/17/99 BusSBusTurboChannelMicroChannelPCI OriginatorSunDECIBMIntel Clock Rate (MHz)16-2512.5-25async33 AddressingVirtualPhysicalPhysicalPhysical Data Sizes (bits)8,16,328,16,24,328,16,24,32,64 8,16,24,32,64 MasterMultiSingleMultiMulti ArbitrationCentralCentralCentralCentral 32 bit read (MB/s)33252033 Peak (MB/s)898475111 (222) Max Power (W)16261325 1993 Backplane/IO Bus Survey

58. CS252/Kubiatowicz Lec 23.58 11/17/99 Examples –graphics –fast networks Limited number of devices Data transfer bursts at full rate DMA transfers important –small controller spools stream of bytes to or from memory Either side may need to squelch transfer –buffers fill up High Speed I/O Bus

59. CS252/Kubiatowicz Lec 23.59 11/17/99 All signals sampled on rising edge Centralized Parallel Arbitration –overlapped with previous transaction All transfers are (unlimited) bursts Address phase starts by asserting FRAME# Next cycle “initiator” asserts cmd and address Data transfers happen on when –IRDY# asserted by master when ready to transfer data –TRDY# asserted by target when ready to transfer data –transfer when both asserted on rising edge FRAME# deasserted when master intends to complete only one more data transfer PCI Read/Write Transactions

60. CS252/Kubiatowicz Lec 23.60 11/17/99 – Turn-around cycle on any signal driven by more than one agent PCI Read Transaction

61. CS252/Kubiatowicz Lec 23.61 11/17/99 PCI Write Transaction

62. CS252/Kubiatowicz Lec 23.62 11/17/99 Push bus efficiency toward 100% under common simple usage –like RISC Bus Parking –retain bus grant for previous master until another makes request –granted master can start next transfer without arbitration Arbitrary Burst length –initiator and target can exert flow control with xRDY –target can disconnect request with STOP (abort or retry) –master can disconnect by deasserting FRAME –arbiter can disconnect by deasserting GNT Delayed (pended, split-phase) transactions –free the bus after request to slow device PCI Optimizations

63. CS252/Kubiatowicz Lec 23.63 11/17/99 Summary Buses are an important technique for building large-scale systems –Their speed is critically dependent on factors such as length, number of devices, etc. –Critically limited by capacitance –Tricks: esoteric drive technology such as GTL Important terminology: –Master: The device that can initiate new transactions –Slaves: Devices that respond to the master Two types of bus timing: –Synchronous: bus includes clock –Asynchronous: no clock, just REQ/ACK strobing Direct Memory Access (dma) allows fast, burst transfer into processor’s memory: –Processor’s memory acts like a slave –Probably requires some form of cache-coherence so that DMA’ed memory can be invalidated from cache.

64. CS252/Kubiatowicz Lec 23.64 11/17/99 Summary of Bus Options OptionHigh performanceLow cost Bus widthSeparate addressMultiplex address & data lines& data lines Data widthWider is fasterNarrower is cheaper (e.g., 32 bits)(e.g., 8 bits) Transfer sizeMultiple words hasSingle-word transfer less bus overheadis simpler Bus mastersMultipleSingle master (requires arbitration)(no arbitration) ClockingSynchronousAsynchronous

65. CS252/Kubiatowicz Lec 23.65 11/17/99 Processor Interface Issues Processor interface –Interrupts –Memory mapped I/O I/O Control Structures –Polling –Interrupts –DMA –I/O Controllers –I/O Processors Capacity, Access Time, Bandwidth Interconnections –Busses

66. CS252/Kubiatowicz Lec 23.66 11/17/99 I/O Interface Independent I/O Bus CPU Interface Peripheral Memory memory bus Seperate I/O instructions (in,out) CPU Interface Peripheral Memory Lines distinguish between I/O and memory transfers common memory & I/O bus VME bus Multibus-II Nubus 40 Mbytes/sec optimistically 10 MIP processor completely saturates the bus!

67. CS252/Kubiatowicz Lec 23.67 11/17/99 Memory Mapped I/O Single Memory & I/O Bus No Separate I/O Instructions CPU Interface Peripheral Memory ROM RAM I/O $ CPU L2 $ Memory Bus MemoryBus Adaptor I/O bus

68. CS252/Kubiatowicz Lec 23.68 11/17/99 Programmed I/O (Polling) CPU IOC device Memory Is the data ready? read data store data yes no done? no yes busy wait loop not an efficient way to use the CPU unless the device is very fast! but checks for I/O completion can be dispersed among computationally intensive code

69. CS252/Kubiatowicz Lec 23.69 11/17/99 Interrupt Driven Data Transfer CPU IOC device Memory add sub and or nop read store... rti memory user program (1) I/O interrupt (2) save PC (3) interrupt service addr interrupt service routine (4) Device xfer rate = 10 MBytes/sec => 0.1 x 10 sec/byte => 0.1 µsec/byte => 1000 bytes = 100 µsec 1000 transfers x 100 µsecs = 100 ms = 0.1 CPU seconds -6 User program progress only halted during actual transfer 1000 transfers at 1 ms each: 1000 interrupts @ 2 µsec per interrupt 1000 interrupt service @ 98 µsec each = 0.1 CPU seconds Still far from device transfer rate! 1/2 in interrupt overhead

70. CS252/Kubiatowicz Lec 23.70 11/17/99 Direct Memory Access CPU IOC device Memory DMAC Time to do 1000 xfers at 1 msec each: 1 DMA set-up sequence @ 50 µsec 1 interrupt @ 2 µsec 1 interrupt service sequence @ 48 µsec.0001 second of CPU time CPU sends a starting address, direction, and length count to DMAC. Then issues "start". DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory. 0 ROM RAM Peripherals DMAC n Memory Mapped I/O

71. CS252/Kubiatowicz Lec 23.71 11/17/99 Input/Output Processors CPU IOP Mem D1 D2 Dn... main memory bus I/O bus CPU IOP issues instruction to IOP interrupts when done (1) memory (2) (3) (4) Device to/from memory transfers are controlled by the IOP directly. IOP steals memory cycles. OP Device Address target device where cmnds are looks in memory for commands OP Addr Cnt Other what to do where to put data how much special requests

72. CS252/Kubiatowicz Lec 23.72 11/17/99 Relationship to Processor Architecture I/O instructions have largely disappeared Interrupt vectors have been replaced by jump tables PC <- M [ IVA + interrupt number ] PC <- IVA + interrupt number Interrupts: –Stack replaced by shadow registers –Handler saves registers and re-enables higher priority int's –Interrupt types reduced in number; handler must query interrupt controller

73. CS252/Kubiatowicz Lec 23.73 11/17/99 Relationship to Processor Architecture Caches required for processor performance cause problems for I/O –Flushing is expensive, I/O polutes cache –Solution is borrowed from shared memory multiprocessors "snooping" Virtual memory frustrates DMA Load/store architecture at odds with atomic operations – load locked, store conditional Stateful processors hard to context switch

74. CS252/Kubiatowicz Lec 23.74 11/17/99 Summary Disk industry growing rapidly, improves: –bandwidth 40%/yr, –areal density 60%/year, $/MB faster? queue + controller + seek + rotate + transfer Advertised average seek time benchmark much greater than average seek time in practice Response time vs. Bandwidth tradeoffs Queueing theory: or Value of faster response time: –0.7sec off response saves 4.9 sec and 2.0 sec (70%) total time per transaction => greater productivity –everyone gets more done with faster response, but novice with fast response = expert with slow

75. CS252/Kubiatowicz Lec 23.75 11/17/99 Summary: Relationship to Processor Architecture I/O instructions have disappeared Interrupt vectors have been replaced by jump tables Interrupt stack replaced by shadow registers Interrupt types reduced in number Caches required for processor performance cause problems for I/O Virtual memory frustrates DMA Load/store architecture at odds with atomic operations Stateful processors hard to context switch