1. Operational-Amplifier and Data-Converter Circuits1

2. sedr42021_0901.jpg
Figure 9.1 The basic two-stage CMOS op-amp configuration.
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3. sedr42021_0902.jpg
Figure 9.2 Small-signal equivalent circuit for the op amp in Fig. 9.1.
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4. sedr42021_0903.jpg
Figure 9.3 An approximate high-frequency equivalent circuit of the two-stage op amp. This circuit applies for frequencies fP1.
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Figure 9.4 Typical frequency response of the two-stage op amp.
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Figure 9.5 Small-signal equivalent circuit of the op amp in Fig. 9.1 with a resistance R included in series with CC.
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Figure 9.6 A unity-gain follower with a large step input. Since the output voltage cannot change immediately, a large differential voltage appears between the op-amp input terminals.
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8. sedr42021_0907.jpg
Figure 9.7 Model of the two-stage CMOS op amp of Fig. 9.1 when a large differential voltage is applied.
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Figure 9.8 Structure of the folded-cascode CMOS op amp.
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Figure 9.9 A more complete circuit for the folded-cascode CMOS amplifier of Fig. 9.8.
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Figure Small-signal equivalent circuit of the folded-cascode CMOS amplifier. Note that this circuit is in effect an operational transconductance amplifier (OTA).
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12. sedr42021_0911.jpg
Figure A folded-cascode op amp that employs two parallel complementary input stages to achieve rail-to-rail input common-mode operation. Note that the two “+” terminals are connected together and the two “–” terminals are connected together.
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13. sedr42021_0912a.jpg
Figure (a) Cascode current mirror with the voltages at all nodes indicated. Note that the minimum voltage allowed at the output is Vt + VOV. (b) A modification of the cascode mirror that results in the reduction of the minimum output voltage to VOV. This is the wide-swing current mirror.
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14. sedr42021_e0908.jpg
Figure E9.8
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15. sedr42021_0913.jpg
Figure The 741 op-amp circuit. Q11, Q12, and R5 generate a reference bias current, IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuits and are normally cut off.
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16. sedr42021_0914a.jpg
Figure 9.14 (a) The emitter follower is a class A output stage. (b) Class B output stage.
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17. sedr42021_0914c.jpg
Figure (Continued) (c) The output of a class B output stage fed with an input sinusoid. Observe the crossover distortion. (d) Class AB output stage.
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18. sedr42021_e0910.jpg
Figure E9.10
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19. sedr42021_0915.jpg Figure 9.15 The Widlar current source.
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20. sedr42021_0916.jpg Figure 9.16 The dc analysis of the 741 input stage.
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21. sedr42021_0917.jpg
Figure The dc analysis of the 741 input stage, continued.
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Figure The 741 output stage without the short-circuit protection devices.
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Figure Small-signal analysis of the 741 input stage.
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Figure The load circuit of the input stage fed by the two complementary current signals generated by Q1 through Q4 in Fig Circled numbers indicate the order of the analysis steps.
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Figure Simplified circuits for finding the two components of the output resistance Ro1 of the first stage.
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Figure Small-signal equivalent circuit for the input stage of the 741 op amp.
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Figure Input stage with both inputs grounded and a mismatch DR between R1 and R2.
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Figure E9.15
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Figure The 741 second stage prepared for small-signal analysis.
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Figure Small-signal equivalent circuit model of the second stage.
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31. sedr42021_0926.jpg Figure 9.26 Definition of Ro17.
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32. sedr42021_0927.jpg
Figure Thévenin form of the small-signal model of the second stage.
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33. sedr42021_0928.jpg Figure 9.28 The 741 output stage.
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34. sedr42021_0929.jpg
Figure Model for the 741 output stage. This model is based on the amplifier equivalent circuit presented in Table 5.5 as “Equivalent Circuit C.”
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Figure Circuit for finding the output resistance Rout.
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Figure E9.26
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Figure E9.27
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Figure Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain.
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Figure Bode plot for the 741 gain, neglecting nondominant poles.
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Figure A simple model for the 741 based on modeling the second stage as an integrator.
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Figure A unity-gain follower with a large step input. Since the output voltage cannot change instantaneously, a large differential voltage appears between the op-amp input terminals.
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Figure Model for the 741 op amp when a large positive differential signal is applied.
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Figure The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit. The switch closes for a small part (t seconds) of every clock period (T). (b) Input signal waveform. (c) Sampling signal (control signal for the switch). (d) Output signal (to be fed to A/D converter).
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Figure The A/D and D/A converters as circuit blocks.
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Figure The analog samples at the output of a D/A converter are usually fed to a sample-and-hold circuit to obtain the staircase waveform shown. This waveform can then be filtered to obtain the smooth waveform, shown in color. The time delay usually introduced by the filter is not shown.
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Figure An N-bit D/A converter using a binary-weighted resistive ladder network.
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Figure The basic circuit configuration of a DAC utilizing an R-2R ladder network.
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Figure A practical circuit implementation of a DAC utilizing an R-2R ladder network.
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Figure Circuit implementation of switch Sm in the DAC of Fig In a BiCMOS technology, Qms and Qmr can be implemented using MOSFETs, thus avoiding the inaccuracy caused by the base current of BJTs.
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50. sedr42021_0943.jpg Figure 9.43 A simple feedback-type A/D converter.
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51. sedr42021_0944a.jpg
Figure The dual-slope A/D conversion method. Note that vA is assumed to be negative.
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52. sedr42021_0944b.jpg Figure 9.44 (Continued)
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53. sedr42021_0945.jpg
Figure Parallel, simultaneous, or flash A/D conversion.
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Figure Charge-redistribution A/D converter suitable for CMOS implementation: (a) sample phase, (b) hold phase, and (c) charge-redistribution phase.
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55. Figure 9.47 Capture schematic of the two stage CMOS op amp in Example 9.4.
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Figure Magnitude and phase response of the op-amp circuit in Fig. 9.47: R = 1.53 kW, CC = 0 (no frequency compensation), and CC = 0.6 pF (PM = 55°).
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Figure Magnitude and phase response of the op-amp circuit in Fig. 9.47: R = 1.53 kW, CC = 0 (no frequency compensation), and CC = 1.8 pF (PM = 75°).
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58. sedr42021_0950.jpg
Figure Magnitude and phase response of the op-amp circuit in Fig. 9.47: CC = 0.6 pF, R = 1.53 kW (PM = 55°), and R = 3.2 kW (PM = 75°).
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59. sedr42021_0951.jpg
Figure Small-signal step response (for a 10-mV step input) of the op-amp circuit in Fig connected in a unity-gain configuration: PM = 55° (CC = 0.6 pF, R = 1.53 kW) and PM = 75° (CC = 0.6 pF, R = 3.2 kW).
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60. sedr42021_0952.jpg
Figure Large-signal step response (for a 3.3-V step-input) of the op-amp circuit in Fig connected in a unity-gain configuration. The slope of the rising and falling edges of the output waveform correspond to the slew rate of the op amp.
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Figure P9.14
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Figure P9.24
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Figure P9.37
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Figure P9.42
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Figure P9.47
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Figure P9.61
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Figure P9.65
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