1. CS 140L Lecture 9 Professor CK Cheng 6/03/02

2. transistors modules sequential machine system 1.Adders, Muxes 2.F-Fs and counters 3.Finite State Machine 4.System Designs delay, timing design analysis Mealy & Moore Machines System Designs Announcement: Final Monday 11:30-1:30PM List of lab projects Level of designsList of topics

3. CMOS Complementary Logic B A B A NAND B A A B Z = (A+B)’ y = (A B)’ NOR

4. Delay 0 1 MUX cout1 ac abcd MUX d e XOR delay 3 units MUX data input  output 2 units select control 1 unit  output (3) cout2 s Longest path from input to output determines the delay of the module. Clock period is dominated by the longest delay between the registers.

5. C. Tree of modules 0101 l0l0 l1l1 MUX 0101 l2l2 l3l3 s0s0 0101 s1s1

6. Mealy and Moore Machines PS A B E F x=a E,0 F,0 A,0 B,0 x=b B,1 B,0 F,1 A,0 y 0 1 0 1 PS A B0 B1 E F0 F1 x=a E F0 A B0 x=b B1 B0 F1 A Mealy Moore

7. Odd length walking ring counter System Designs, Control & Data Subsystems Responsible for: -Lecture notes -Labs -Exercises