1. CDF sensors processed on 6” wafers OUTLINE: zMaterial description zMasks layout zSensor performances zProcess related problems zConclusions DPG Frühjahrstagung Heidelberg, 15. - 19.März 99 Frank Hartmann Institut für Experimentelle Kernphysik Die CDF Silizium Sensoren in 6“ Technologie

2. Sensor Dimensions zOnly 1 of these sensor can fit in a 4” wafer. z6” = cheaper z6” detectors are even longer than their 4” counterparts zDouble sided zAC coupled zPolySi Biased zSingle metal zCommon P-stops zThickness 300mu

3. Masks layout ISL SVXII L4L2

4. Masks layout (details) P-side N-side

5. Performances zCapacitance zOther parameters:

6. Problems zCoupling capacitor variation across the wafer Uneven metal deposition due to sputtering problems At the edges of the wafer the coupling capacitor falls below specifications

7. Problems zCoupling capacitor breakdown voltage zCreation of pin-holes during operation in test beam z“Weak” coupling capacitor zDifferent “mix” of wet and dry oxide fixed the problem zBreakdown voltage of ISL sensors is currently under test with respect to bonding force at KA

8. Problems zLeaky strips Isolated strips and regions show high leakage current Good strip Leaky strip Most strips are about 1 nA but a few go as high as  A Log scale

9. Problems zLeaky strips zLeaky strips do not affect neighbors zThe noise on them follow predictions (proportional to the square root of the current) zGet worse on the p-side if bias is present (MOS effect) zBreakdown at the Junction edges zVerified with Infrared Camera zPresent even on the n-side when defects are present at the p-stops edges zMost likely related to handling and cleaning conditions  Dust

10. zLeaky strips (2) zDust particles during processing z-> Inaccessible short between implant and p-stop (N-side) z-> fully biased strip z Large effect on p-side strips zDistortion in local field z--> clean room improvements

11. Latest deliveries zProblems got fixed

12. Pin-holes zSVXII and ISL sensors are double side and the bias will be split. zPH is a connection of the implant to input of the PA (virtual GND) zThe PA will then have to deal with a DC coupled strip zCurrent is not driven by the Si but by the bias circuit. zNeighbors channels will be noisy.

13. Pin-holes zOn the N-side the electric field is weak. zThe effect is enhanced and up to 5 channels on each side will show higher noise.

14. Low interstrip resistance First appearance at 2nd step of quality control at KA 100nA 10nA 1G  100k  3M  200k  Leakage current Interstrip resistance Bias resistor Rbias Rint Solve: add. cleaning (charge up ? ) Will it remain good after cleaning ?

15. Conclusions zThe workable area of a 6” wafer is almost twice the one of a 4” wafer z6” Silicon performs as well as 4”. zSwitching from 4” to 6” can be painful but is surely feasible. zRadiation hardness is the same as 4”. zAvailability of material in the market is not an issue.