1. 1 Integrated Management of Power Aware Computing & Communication Technologies PI Meeting Nader Bagherzadeh, Pai H. Chou, Fadi Kurdahi University of California, Irvine, ECE Dept. DARPA Contract F33615-00-1-1719 April 18-20, 2001 San Diego, CA

2. 2 Outline Introduction  Status overview, Application Accomplishments to date  Scheduling  Component power models and simulators  Architecture configuration: Mode Selection Metrics Review of program milestones and goals  Fulfilled: prototype of scheduling/planning tool  Upcoming: integration with COPPER project, dynamic scheduling Future planned evaluation Development platforms, tools, metrics Transition plan.

3. 3 Applications Space  Mars Pathfinder  X-2000 architecture [new] NASA Deep Impact  JPL-led effort, with PowerPC 750 testbed (measures power)  Mission planning, software architecture level ATR  Needs algorithm-level parallelization and arch. (DSP, FPGA) first  System-level pipeline scheduling UCAV  thermal battery scheduling

4. 4 Personnel & teaming plans UC Irvine- Design tools  Nader Bagherzadeh  Pai Chou  Fadi Kurdahi  Jinfeng Liu  Dexin Li  Duan Tran USC- Component power optimization  Jean-Luc Gaudiot  Seong-Won Lee JPL- Applications and benchmarking  Nazeeh Aranki  Nikzad “Benny” Toomarian students student

5. 5 Quad Chart Innovations Component-based power-aware design  Exploit off-the-shelf components & protocols  Best price/performance, reliable, cheap to replace CAD tool for global power policy optimization  Optimal partitioning, scheduling, configuration  Manage entire system, including mechanical & thermal Power-aware reconfigurable architectures  Reusable platform for many missions  Bus segmentation, voltage / frequency scaling Impact Enhanced mission success  More task for the same power  Dramatic reduction in mission completion time Cost saving over a variety of missions  Reusable platform & design techniques  Fast turnaround time by configuration, not redesign Confidence in complex design points  Provably correct functional/power constraints  Retargetable optimization to eliminate overdesign  Power protocol for massive scale Behavior Architecture high-level simulation functional partitioning & scheduling composition operators high-level components behavioral system model busses, protocols system architecture mapping system integration & synthesis static configuration dynamic power management parameterizable components 2Q 00 Kickoff 2Q 01 2Q 02 Static & hybrid optimizations  partitioning / allocation  scheduling  bus segmentation  voltage scaling COTS component library FireWire and I2C bus models Static composition authoring Architecture definition High-level simulation Benchmark Identification Dynamic optimizations  task migration  processor shutdown  bus segmentation  frequency scaling Parameterizable components library Generalized bus models Dynamic reconfiguration authoring Architecture reconfiguration Low-level simulation System benchmarking Year 1Year 2

6. 6 Program Overview Power-aware system-level design  Amdahl's law applies to power as well as performance  Enhance mission success (time, task)  Rapid customization for different missions Design tool  Exploration & evaluation  Optimization& specialization  Technique integration System architecture  Statically configurable  Dynamically adaptive  Use COTS parts & protocols

7. 7 Accomplishments to date Power-aware scheduling -- DEMO  Multiple processors, mechanical, thermal  Min / Max power and timing constraints  Power-aware Gantt chart user interface  Pipelining at system-level Architectural optimization  Bus topology optimization, segmentation  Mode selection for power & timing Component power models and simulators  Performance simulator  Parameterized energy model Interface to COPPER project

8. 8 Power-Aware Scheduling New constraint-based application model [paper at Codes'01]  Min/Max Timing constraints Precedence, subsumes dataflow, general timing, shared resource Dependency across iteration boundaries – loop pipelining Execution delay of tasks – enables frequency/voltage scaling  Power constraints Max power – total power budget Min power – controls power jitter or force utilization of free source System-level, multi-scenario scheduling [paper at DAC'01]  25% Faster while saving 31% energy cost  Exploits "free" power (solar, nuclear min-output) System-level loop pipelining [working papers]  Borrow time and power across iteration boundaries  Aggressive design space exploration by new constraint classification  Achieves 49% speedup and 24% energy reduction

9. 9 Prototype of GUI scheduling tool Power-aware Gantt chart  Time view Timing of all tasks on parallel resources Power consumption of each task  Power view System-level power profile Min/max power constraint, energy cost Interactive scheduling  Automated schedulers – timing, power, loop  Manual intervention – drag & drop Demo available

10. 10 Architectural Configuration Mode selection  Power consumption level (doze, nap, sleep, etc.)  Low power design techniques Clock scaling, voltage scaling Memory/cache configurations, bus encoding Communication protocols, compression, algorithm transformations  Optimize feasible solutions for energy/timing costs  Power, Real time, Inter-resource modes constraints  Constraints between functionality modes and resources modes Functionality mode and resource modes Bus topology optimization  Static clustering and bus partitioning  Dynamic reclustering with shutdown

11. 11 Component power model Performance simulator-drive power estimation  Independent performance simulator and power estimation modules  Modular, can be replaced with other model, extensible Performance simulator  for SMT, up to 8 threads, emulates single thread superscalar CPU  Executes Alpha EV6 binaries, emulates Alpha 21264 Power estimation model  Parameterizable power model for HW modules in microarchitecture  Moving average model for power profile  Inputs microarchitectural params, # accesses (activity factor)

12. 12 Metrics Source-aware energy model  Takes “free energy” into account  Cost for not using free energy Profile-aware  Total energy dependent on consumers’ power profile  Smoothness of power draw Scenario-aware  Cost function tracks external factors (e.g. temperature, solar level)  Stage in mission Timing/performance  Makespan (length of an iteration)  Dynamic planning cost

13. 13 Review of Milestones & Goals Accomplished  UI prototype  Power-aware scheduling [3 papers] Multi-scenario System-level pipelining  Mode selection encompass power mgmt (voltage/freq scaling)  Processor power & simulation models Upcoming  Dynamic optimization Scheduling Architectural reconfiguration  Library of parameterizable bus models  Tool integration IMPACCT tools and library between IMPACCT and COPPER

14. 14 Future planned evaluation Deep Impact from JPL  Mission planning and scheduling example  Image compression (wavelet) algorithm  Architectural mapping JPL Testbed  PPC750 board to measure actual power  PPC750 to simulate instrumentation in real-time  advanced board with real instrumentation Validation through COPPER  Scheduler output fed to COPPER for compilation  Compare estimated power with refined version

15. 15 Technology Transition -- Consystant Design Technologies Beta just released Apr.11  shown at ESC  runs on Linux  will support Solaris, Win2k Extensible system  platform plugin for synthesis  targets Linux, vxWorks, … Simulator  selective focus  coordination centric

16. 16 Development plans Scripting and web-based tool  Jython (Java + Python) for GUI prototype  Core scheduler Modular, detachable from GUI Option to run on separate server or same process as UI  CGI scripts for arch. configuration (unix/web based)  Latest version distributed thru WebCVS Interface with commercial CAD backend  Detailed power estimation tools  Functional simulation with proprietary models Rationale  Open source, runs on any platform  All publicly available development tools  Trivial to install, no compilation, encourage modification

17. 17 http://www.ece.uci.edu/impacct/

18. 18 Application requirements System specification  6 wheel motors  4 steering motors  System health check  Hazard detection Power supply  Battery (non-rechargeable)  Solar panel Power consumption  Digital Computation, imaging, communication, control  Mechanical Driving, steering  Thermal Motors must be heated in low-temperature environment