2. CSE331 W01.1 Irwin Fall 06 PSU CSE 331 Computer Organization and Design Fall 2006 Week 1 Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji Section 2: Feihui Li (www.cse.psu.edu/~feli )www.cse.psu.edu/~feli Adaptado al curso Diseño de Sistemas Digitales. R. Pereira [ slides adapted from D. Patterson slides with additional credits to Y. Xie ]

3. CSE331 W01.2 Irwin Fall 06 PSU Course Administration  Texts:Computer Organization and Design: The Hardware/Software Interface, 3 rd Edition, Patterson and Hennessy

4. CSE331 W01.3 Irwin Fall 06 PSU Course Goals and Structure  Introduction to the major components of a computer system, how they function together in executing a program, how they are designed l MIPS assembler programming using the spim system l VHDL design simulation using the Synopsys VSS tools  Prerequisite: CSE 271 (INTRO TO DIGITAL SYSTEMS. Introduction to logic design and digital systems, boolean algebra, and introduction to combinatorial and sequential circuit design and analysis)  En el curso Estructura de Microprocesadores aprenderán otro lenguaje ensamblador (IA80x86)

5. CSE331 W01.4 Irwin Fall 06 PSU spim Assembler and Simulator  spim is a simulator that runs MIPS32 assembly language programs l It provides a simple assembler, debugger and a simple set of operating system services l It implements both a simple, terminal-style interface (spim) and a visual windowing interface (xspim and PCSpim)  Available as l xspim (or spim) for unix, linux, and Mac OS X -installed on the CSE unix/linux machines in the lab l PCSpim (or spim) for Windows (NT, 2000, XP) -can be downloaded and installed on your own PC from www.cs.wisc.edu/~larus/SPIM

6. CSE331 W01.5 Irwin Fall 06 PSU What You Should Already Know  How to write, compile and run programs in a higher level language (C, C++, Java, …)  How to create, organize, and edit files and run programs on Unix  How to represent and operate on positive and negative numbers in binary form (two’s complement, sign magnitude, etc.)  Logic design l How to design of combinational and sequential components (Boolean algebra, logic minimization, technology mapping, decoders and multiplexors, latches and flipflops, registers, mealy/moore finite state machines, state assignment and minimization, etc.) l How to use a logic schematic capture and simulation tool (e.g., LogicWorks)

7. CSE331 W01.6 Irwin Fall 06 PSU Schedul e  This week’s material l Course introduction, basics of a computer system, introduction to SPIM -Reading assignment – PH 1.1 through 1.3 and A.9 through A.10  Next week’s material l Introduction to MIPS assembler, adds/loads/stores -Reading assignment - PH 2.1 through 2.4

8. CSE331 W01.7 Irwin Fall 06 PSU The Evolution of Computer Hardware  When was the first transistor invented?

9. CSE331 W01.8 Irwin Fall 06 PSU The Evolution of Computer Hardware  When was the first transistor invented? l Modern-day electronics began with the invention in 1947 of the transfer resistor - the bi-polar transistor - by Bardeen et.al at Bell Laboratories

10. CSE331 W01.9 Irwin Fall 06 PSU The Evolution of Computer Hardware  When was the first IC (integrated circuit) invented?

11. CSE331 W01.10 Irwin Fall 06 PSU The Evolution of Computer Hardware  When was the first IC (integrated circuit) invented? l In 1958 the IC was born when Jack Kilby at Texas Instruments successfully interconnected, by hand, several transistors, resistors and capacitors on a single substrate

12. CSE331 W01.11 Irwin Fall 06 PSU The Underlying Technologies YearTechnologyRelative Pref/Unit Cost 1951Vacuum Tube1 1965Transistor35 1975Integrated Circuit (IC)900 1995Very Large Scale IC (VLSI)2,400,000 2005Ultra VLSI6,200,000,000 What if technology in the transportation industry advanced at the same rate?

13. CSE331 W01.12 Irwin Fall 06 PSU The PowerPC 750  Introduced in 1999  3.65M transistors  366 MHz clock rate  40 mm 2 die size  250nm technology

14. CSE331 W01.13 Irwin Fall 06 PSU Technology Outlook High Volume Manufacturing 20042006200820102012201420162018 Technology Node (nm) 906545322216118 Integration Capacity (BT) 248163264128256 Delay = CV/I scaling 0.7~0.7>0.7Delay scaling will slow down Energy/Logic Op scaling >0.35>0.5 Energy scaling will slow down Bulk Planar CMOS High Probability Low Probability Alternate, 3G etc Low Probability High Probability Variability Medium High Very High ILD (K) ~3<3 Reduce slowly towards 2 to 2.5 RC Delay 11111111 Metal Layers 6-77-88-90.5 to 1 layer per generation

15. CSE331 W01.14 Irwin Fall 06 PSU Impacts of Advancing Technology  Processor l logic capacity: increases about 30% per year l performance: 2x every 1.5 years  Memory l DRAM capacity: 4x every 3 years, about 60% per year l memory speed: 1.5x every 10 years l cost per bit: decreases about 25% per year  Disk l capacity: increases about 60% per year

16. CSE331 W01.15 Irwin Fall 06 PSU Growth Capacity of DRAM Chips K = 1024 (2 10 ) In recent years growth rate has slowed to 2x every 2 year

17. CSE331 W01.16 Irwin Fall 06 PSU Computer Organization and Design  This course is all about how computers work  But what do we mean by a computer? l Different types: embedded, laptop, desktop, server l Different uses: automobiles, graphics, finance, genomics… l Different manufacturers: Intel, Apple, IBM, Sony, Sun… l Different underlying technologies and different costs !  Analogy: Consider a course on “automotive vehicles” l Many similarities from vehicle to vehicle (e.g., wheels) l Huge differences from vehicle to vehicle (e.g., gas vs. electric)  Best way to learn: l Focus on a specific instance and learn how it works l While learning general principles and historical perspectives

18. CSE331 W01.17 Irwin Fall 06 PSU Embedded Computers in You Car

19. CSE331 W01.18 Irwin Fall 06 PSU Growth of Sales of Embedded Computers

20. CSE331 W01.19 Irwin Fall 06 PSU Why Learn This Stuff?  You want to call yourself a “computer scientist/engineer”  You want to build HW/SW people use (so need performance)  You need to make a purchasing decision or offer “expert” advice  Both hardware and software affect performance l Algorithm determines number of source-level statements l Language/compiler/architecture determine the number of machine-level instructions -(Chapter 2 and 3) l Processor/memory determine how fast machine-level instructions are executed -(Chapter 5, 6, and 7)

21. CSE331 W01.20 Irwin Fall 06 PSU What is a Computer?  Components: l processor (datapath, control) l input (mouse, keyboard) l output (display, printer) l memory (cache (SRAM), main memory (DRAM), disk drive, CD/DVD) l network  Our primary focus: the processor (datapath and control) l Implemented using millions of transistors l Impossible to understand by looking at each transistor l We need abstraction!

22. CSE331 W01.21 Irwin Fall 06 PSU Major Components of a Computer

23. CSE331 W01.22 Irwin Fall 06 PSU Head’s Up  This week’s material l Course introduction -Reading assignment – PH 1.1 through 1.3 and A.9 through A.10  Reminders l Make sure your unix account is operational; change your password to something you can remember and that is secure (must be six to eight alphanumeric characters) l Question/comments about the system go to helpdesk@cse.psu.edu ; questions about the programming assignments go to the course TAs helpdesk@cse.psu.edu l Check out the course homepage at ANGEL!  Next week’s material l Introduction to MIPS assembler -Reading assignment - PH 2.1 through 3.3, 3.4, and 3.7

24. CSE331 W01.23 Irwin Fall 06 PSU End of Lecture #1

25. CSE331 W01.24 Irwin Fall 06 PSU Quote for the Day “We all make mistakes … Our designs have to work flawlessly despite us.” Bob Colwell The Pentium Chronicles

26. CSE331 W01.25 Irwin Fall 06 PSU Below the Program  High-level language program (in C) swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; )  Assembly language program (for MIPS) swap:sll$2, $5, 2 add$2, $4, $2 lw$15, 0($2) lw$16, 4($2) sw$16, 0($2) sw$15, 4($2) jr$31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000...

27. CSE331 W01.26 Irwin Fall 06 PSU Below the Program  High-level language program (in C) swap (int v[], int k) (int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; )  Assembly language program (for MIPS) swap:sll$2, $5, 2 add$2, $4, $2 lw$15, 0($2) lw$16, 4($2) sw$16, 0($2) sw$15, 4($2) jr$31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000... C compilerassembler one-to-many one-to-one

28. CSE331 W01.27 Irwin Fall 06 PSU Advantages of Higher-Level Languages ?

29. CSE331 W01.28 Irwin Fall 06 PSU Advantages of Higher-Level Languages ?  Higher-level languages  As a result, very little programming is done today at the assembler level l Allow the programmer to think in a more natural language and for their intended use (Fortran for scientific computation, Cobol for business programming, Lisp for symbol manipulation, Java for web programming, …) l Improve programmer productivity – more understandable code that is easier to debug and validate l Improve program maintainability l Allow programs to be independent of the computer on which they are developed (compilers and assemblers can translate high-level language programs to the binary instructions of any machine) l Emergence of optimizing compilers that produce very efficient assembly code optimized for the target machine

30. CSE331 W01.29 Irwin Fall 06 PSU Machine Organization  Capabilities and performance characteristics of the principal Functional Units (FUs) l e.g., register file, ALU, multiplexors, memories,...  The ways those FUs are interconnected l e.g., buses  Logic and means by which information flow between FUs is controlled  The machine’s Instruction Set Architecture (ISA)  Register Transfer Level (RTL) machine description

31. CSE331 W01.30 Irwin Fall 06 PSU ISA Sales

32. CSE331 W01.31 Irwin Fall 06 PSU Major Components of a Computer Processor Control Datapath Memory Devices Input Output Network

33. CSE331 W01.32 Irwin Fall 06 PSU Below the Program C compilerassembler  High-level language program (in C) swap (int v[], int k)...  Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

34. CSE331 W01.33 Irwin Fall 06 PSU Below the Program C compilerassembler  High-level language program (in C) swap (int v[], int k)...  Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31  Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

35. CSE331 W01.34 Irwin Fall 06 PSU Input Device Inputs Object Code Processor Control Datapath Memory 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Devices Input Output Network

36. CSE331 W01.35 Irwin Fall 06 PSU Object Code Stored in Memory Processor Control Datapath Memory 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Devices Input Output Network

37. CSE331 W01.36 Irwin Fall 06 PSU Processor Fetches an Instruction Processor Control Datapath Memory 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Processor fetches an instruction from memory Devices Input Output Network

38. CSE331 W01.37 Irwin Fall 06 PSU Control Decodes the Instruction Processor Control Datapath Memory 000000 00100 00010 0001000000100000 Control decodes the instruction to determine what to execute Devices Input Output Network

39. CSE331 W01.38 Irwin Fall 06 PSU Datapath Executes the Instruction Processor Control Datapath Memory contents Reg #4 ADD contents Reg #2 results put in Reg #2 Datapath executes the instruction as directed by control 000000 00100 00010 0001000000100000 Devices Input Output Network

40. CSE331 W01.39 Irwin Fall 06 PSU What Happens Next? Processor Control Datapath Memory 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Devices Input Output Network

41. CSE331 W01.40 Irwin Fall 06 PSU What Happens Next? Processor Control Datapath Memory 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 FetchDecodeExec Devices Input Output Network

42. CSE331 W01.41 Irwin Fall 06 PSU Processor Fetches the Next Instruction Processor Control Datapath Memory 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000 Processor fetches the next instruction from memory How does it know which location in memory to fetch from next? Devices Input Output Network

43. CSE331 W01.42 Irwin Fall 06 PSU Processor Organization  Control needs to have circuitry to  Datapath needs to have circuitry to

44. CSE331 W01.43 Irwin Fall 06 PSU Processor Organization  Control needs to have circuitry to What location does it load from and store to? l Decide which is the next instruction and input it from memory l Decode the instruction l Issue signals that control the way information flows between datapath components l Control what operations the datapath’s functional units perform l Execute instructions - functional units (e.g., adder) and storage locations (e.g., register file) l Interconnect the functional units so that the instructions can be executed as required l Load data from and store data to memory  Datapath needs to have circuitry to

45. CSE331 W01.44 Irwin Fall 06 PSU Output Data Stored in Memory Processor Control Datapath Memory 00000100010100000000000000000000 00000000010011110000000000000100 00000011111000000000000000001000 At program completion the data to be output resides in memory Devices Input Output Network

46. CSE331 W01.45 Irwin Fall 06 PSU Output Device Outputs Data Processor Control Datapath Memory 00000100010100000000000000000000 00000000010011110000000000000100 00000011111000000000000000001000 Devices Input Output Network

47. CSE331 W01.46 Irwin Fall 06 PSU The Instruction Set Architecture (ISA) instruction set architecture software hardware The interface description separating the software and hardware

48. CSE331 W01.47 Irwin Fall 06 PSU The MIPS ISA  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special R0 - R31 PC HI LO OP rs rt rdsafunct rs rt immediate jump target  3 Instruction Formats: all 32 bits wide Registers Q: How many already familiar with MIPS ISA?

49. CSE331 W01.48 Irwin Fall 06 PSU How Do the Pieces Fit Together? I/O system Processor Compiler Operating System Applications Digital Design Circuit Design Instruction Set Architecture Firmware  Coordination of many levels of abstraction  Under a rapidly changing set of forces  Design, measurement, and evaluation Memory system Datapath & Control network

50. CSE331 W01.49 Irwin Fall 06 PSU How Do the Pieces Fit Together? I/O system Processor Compiler Operating System Applications Digital Design Circuit Design Instruction Set Architecture Firmware  Coordination of many levels of abstraction  Under a rapidly changing set of forces  Design, measurement, and evaluation Memory system Datapath & Control network CSE 411 CSE 421 CSE 331 & 431 CSE 447 & 477 CSE 271 & 471 CSE 458

51. CSE331 W01.50 Irwin Fall 06 PSU Review and Reminder  Next week’s material l Introduction to MIPS assembler -Reading assignment - PH 2.1 through 2.4  Other reminders l Install PCSpim on your laptop