1. 1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 8 MAD MAC 525 22 nd March, 2006 Functional Block and Simulations W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2. 2 MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small blocks Large block layouts, extractions, LVS, simulations (in progress) Spring Break  To be done  Full chip layout and simulation

3. 3 RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Ovf Checker Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input Output 16 Reg Y 15 1 1 1 Block Diagram

4. 4 Design Decisions Pipelining Stages: Add another stage in multiplier since adder is very fast. –Projected speed is at least 400 MHz –Exceeds the design goal of 300MHz

5. 5 Pipelining Stages Multiplier Align C Reg A Reg B Exp Calc Reg C Pipeline Reg Adder Ld Zero Pipeline Reg Normalize Round Reg Y Pipeline Reg Overflow checker Pipeline Reg

6. 6 Timing Diagram Pipeline stage 1 Pipeline stage 2 Pipeline stage 3 Pipeline stage 4 Pipeline stage 5 Multiplier lower 7 outputs Multiplier mid 4 outputs Multiplier top 11 outputs AdderNormalize Exponent calculator Holds exponent calculator? AlignZero Counter Round Holds exponent calculator bits Overflow Checker

7. 7 New Floorplan

8. 8 Design Decisions Pipelining Stages: Add another stage in multiplier since adder is very fast. –Projected speed is at least 400 MHz –Exceeds the design goal of 300MHz Optimized adder design which implements carry look ahead architecture –Propagation delay of around 800ps (1250MHz) –Bit slicing the adder in the layout

9. 9 Adder Schematic

10. 10 Adder Schematic Simulation

11. 11 Adder Bit Slice Layout

12. 12 Transisto r Count Area in um 2 Prop. Delay Power in mW (350MHz) Multiplier3600165604.64n8.5 Exponents738 3800942p1.608 Align500 2990637p0.393 Adder3174158701n5.236 Leading 0364 1222551p0.857 Normalize942 3176430p2.291 Round462 2310948p0.631 OvfCheck100 500475p0.13 Registers1850 9200120p- Total 1173055628--

13. 13 Optimized Round Schematic

14. 14 Normalize Layout

15. 15 Align Layout

16. 16 Align Simulation

17. 17 Exponents progress…

18. 18 Questions??