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1 Integrating Logic Retiming and Register Placement Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay Yih-Chih Chou, and Youn-Long Lin Department of Computer Science Tsing Hua University Hsin-Chu, Taiwan, R.O.C.
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2 Outline Motivation Key problems Proposed System flow Retiming algorithm Interconnection delay estimation Register placement Experimental results Conclusion and future work
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3 Motivation Wiring delay dominance in VDSM era. Retiming cannot ignore wiring delay. Wiring delay is layout dependent. retiming layout ? ?
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4 Key Problems Post-Layout Retiming incorporating interconnection delay Interconnection delay estimation –delay change due to register insertion or removal –tree topology dependence Post-retiming (register) placement
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5 Retiming Incorporating Interconnection Delay Given estimated interconnection delay, find a legal retiming such that the clock period of the circuit is optimal. Delays a, b, and c must be estimated before retiming. a bc
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6 Previous Work Soyata and Friedman (ICCAD’94): –branch-and-bound method –optimal solution in the first time –time consuming Lalgudi and Papaefthymiou (DAC’95): –integer linear programming method optimal solution –polynomial time algorithm if the circuit is one-way extendible
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7 Interconnection Delay Estimation Given layout –Estimate wiring delay change due to register insertion or removal –Tree-topology dependence of wiring delay
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8 Effect of Register Insertion or Removal on Wiring Delay (a) adding a register (b) deleting a register (c) an unchanged wire
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9 Tree-Topology-Dependence of Wiring Delay
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10 Post-Retiming (Register) Placement Post-retiming layout refinement to meet timing goal Need specific technique
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11 Proposed System Flow
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12 Retiming Incorporating Wiring Delay Extend a previous algorithm (proposed in pp.384-393, SASIMI’93) to incorporate the interconnection delay. Efficient, optimal for circuits satisfy the path monotonicity constraints.
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13 Interconnection Delay Estimation (a) adding a register (b) deleting a register (c) an unchanged wire
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14 Predicting Location for the Inserted Register In the slot nearest the geometric center among its fan-in and fan-out cells. G40392 G42709 G42767
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15 Tree-Topology Selection Choosing the one with the most delay.
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16 Post-Retiming (Register) Placement Freeze all combinational cells Relocate all registers in 3 steps –Slack assignment –Placement range calculation –Simultaneous register to slot assignment
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17 Slack Assignment
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18 Placement Range G40391 G42612 G42552 0.172 0.215 0.110
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19 Simultaneous Register Place- ment by Bipartite Matching G161 G164 G167 G170 G173 G176 G180 G183 G188 G191 G194 G170 G173 G176 G180 G183 G188 G191 G218 register slot
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20 Experimental Results
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21 Conclusion Retiming and layout are combined for the first time. Three sub-problems: retiming incorporating interconnection delay, delay estimation, and post-retiming (register) placement.
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22 Future Work Tightly coupled simultaneous placement and retiming Retiming considering wire delay and number of registers Using more advanced delay model and considering more VDSM effects
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