1. 1 Product Overview Voice Specific Analog-to-Digital Conversion Chip Meeting demands of high quality voice applications such as: Digital Telephony, Digital Hearing Aids and VOIP. TEAM W3: Digital Voice Processor 525 Jarrett Avery (W3-1) Sean Baker (W3-2) Huiyi Lim (W3-3) Sherif Morcos (W3-4) Amar Sharma (W3-5) Date: 5/3/2006 Final Presentation Design Manager: Abhishek Jajoo

2. 2 Final Presentation Agenda  Product Background & Marketing  Jarrett Avery  Algorithm & Design Process  Sean Baker  Floorplan Evolution & Component Layout  Sherif Morcos  Top Level Layout & Digital Verification  Amar Sharma  Analog/Overall Verification, Specs, & Summary  Huiyi Lim

3. 3 Product Background & Marketing Jarrett Avery

4. 4 Product Background  Find a Customer  Complement Current Market Trends  Develop for Multiple Applications  Design a Comprehensive Product  Fulfill classroom design goals  Include useful features and benefits  Use Talents of a Diverse Team  Analog and Digital Design Skills

5. 5 Voice Market  Target Customers  IP Telephone Providers  Vonage, Skype, and CRM  Government and Security Agencies  Hearing Aid Producers  Goal of the Product  Better-Cheaper Telephone Service (VOIP)  Secure Private Telephony  Custom Hearing Aids for Specific Conditions  More Accurate Speech to Text

6. 6 Specific Applications  Communication Devices  Voice Over IP Handsets  Encrypted Telephony  Digital Hearing Aids  Speech Recognition

7. 7 Why Choose DVP-525  Better than other products on the market  Superior Features Include:  Precision 1 st Order Delta Sigma ADC  Integrated Butterworth Low-Pass Filter  Built on 180 nm Technology  Includes a Min/Max Input Indicator  Important Benefits:  Low Power Design – For mobile applications  Small Foot Print – Fits into larger signal chains  Resilience to Circuit Noise – Optimized to reduce interference

8. 8 Delta Sigma (ΔΣ) Design  Advantages  Accurate Conversion, oversamples the input signal and filters the desired signal band.  Filters off unwanted noise in the signal  Good design for audio applications  Consists of two part design for the team  Analog Modulator  Digital Decimator

9. 9 Algorithm & Design Process Sean Baker

10. 10 ΔΣ Algorithm (Analog) Lowpass Filter Delta Sigma Modulator Input from outside world Bitstream into sinc filter Filtered analog signal

11. 11 ΔΣ Algorithm (Digital) Sinc Filter Peak Input Indicator Bitstream from modulator Nyquist clock Digital output Digital Output Max / Min output Oversampled clock

12. 12 Top Level Schematic

13. 13 Design Process Integrate & Simulate Architecture Behavioral Circuit Elements Topologies Schematic Layout Extract Architecture Behavioral Verilog Structural Verilog Schematic Layout Extract

14. 14 Design Process (cont.)  Both teams worked somewhat independently  Analog side used behavioral sinc filter  Digital side used simulated inputs  When either team takes a major step, make sure everything still works  Compare structural to behavioral, schematic to structural, etc  When possible, put the two halves together

15. 15 Major Design Decisions Focus on voice specific frequencies: 0 – 10 KHz  Sets Nyquist clock at 20 KHz  First order modulator  Oversampling rate of 256  Sets oversampled clock at 5.12 MHz  Second order sinc filter  Lth order modulator requires L+1 order sinc filter  16 bit resolution  Mth order sinc filter requires [ M*log 2 (OSR) ] bits  Designed with NCSU design kit  Might’ve been easier to use GPDK, if used from the start

16. 16 Floorplan Evolution Component Layout Sherif Morcos

17. 17 Floorplan Evolution  Floorplan changed several times  Original floorplan:  18 bit decimator and 2 nd order modulator  Overall chip area = 335 μ m x 230 μ m = 77,000 μ m²  Modified floorplan  2 nd order analog modulator with enormous resistors and capacitors (about 150 μ m x 50 μm = 7,500 μm² each)  3 rd order 24-bit digital sinc filter plus PII module and clock divider (14,500 transistors)

18. 18 Original Floorplan

19. 19 Floorplan Evolution (cont’d)  Final floorplan:  With previous floorplan, might have violated area constraint of 300,000 μ m²  Change to analog modulator reduced size of design  Determined that passive elements could be reduced in size considerably  After modifications, floorplan area was estimated at about 400 μ m x 340 μ m = 136,000 μ m²  Final layout grew slightly to 500 μ m x 378 μ m = 189,000 μ m² with slight increase in size of passive components

20. 20 Final Floorplan

21. 21 ΔΣ Modulator Transistor - Layout 17 Analog Transistors Differential Op Amp Comparator D Flip Flop

22. 22 Decimator – Layout Sinc2 Filter PII Function 256 Clock Divider

23. 23 Isolation Rings

24. 24 Top Level Layout & Digital Verification Amar Sharma

25. 25 Final Top Level Layout

26. 26 Final Floorplan Modulator Low Pass Filter Clock Divider PII Sinc Filter

27. 27 Data Flow – Top Level Layout Wait Period 1-Bit Stream Min 16-BitsOut Max Low Pass Components Delta Sigma Modulator Components PII Sinc Filter CLK Divider Analog Input Filtered Signal

28. 28 Poly & Active Poly density: 23.92% Active / Well density: 1.01%

29. 29 Metal 1 Metal 1 density: 25.33%

30. 30 Metal 2 Metal 2 density: 23.89%

31. 31 Metal 3 Metal 3 density: 22.53%

32. 32 Metal 4 Metal 4 density: 0.68%

33. 33 Digital Verification  All digital components functionally verified previously  No timing analysis required  Clocks domains are 5.12 MHz and 20 KHz  Critical path (two 16 bit adders) are located in 20 KHz domain  Optimization - Main focus to ensure signal integrity  Initial layouts had outputs not reaching full-rail  Optimizations widened Vdd and Gnd lines  Outputs now swing full-rail

34. 34 High Output Levels BeforeAfter

35. 35 Sinc Filter extractedRC Output

36. 36 PII extractedRC Output (Max)

37. 37 PII extractedRC Output (Min)

38. 38 Analog/Overall Verification Specs & Summary Huiyi Lim

39. 39 Analog Verification  Analog half is simulated as ExtractedRC  Input is a weighted sum of frequencies found in the human voice  Output of analog half is a bitstream  To make sense of it, behavioral decimator is used  To get proper results, simulator must be set to be as accurate as possible  Greatly increases running time of simulation

40. 40 Analog Verification (cont.)

41. 41 Overall Verification  Extracted the lowpass filter, modulator, and sinc filter together, then simulated  Used actual outputs from clock divider in simulation without including it in simulation  Input is a simple 2 KHz sine wave

42. 42 Overall Verification (cont.)

43. 43 Chip Specs ModulePowerTransistorsArea Transistor Density Modulator Shares 235.4 uW 32 40,390 um^2.00079 Lowpass Shares 235.4 uW 0 55,235 um^2 N/A Clock Divider 7.138 uW 334 1,728 um^2.1932 Sinc Filter Shares 235.4 uW (consumes 15.33 uW itself) 3,296 18,686 um^2.1764 PII 292 nW 2782 17,912 um^2.1553 Total 242.8 uW 6,444 187,500 um^2.0346 Aspect Ratio: 1.3 Input Bandwidth: 0 – 10 KHz Oversampling rate: 256 16 bit resolution

44. 44 Pin Specs  Inputs  2 Analog Inputs  12 Wait Period Inputs  Oversampled Clock Input  Outputs  16bit Output Pins  16bit Min Pins  16bit Max Pins  Other  Vdd & Gnd Pins

45. 45 Product Summary  Achieved first working mixed signal design in 18-525 history  Met course objectives  Low power design (242 μ W)  Small size (500 μ m x 370 μ m)  Under 100 pins (55 total pins)  Developed a practical & marketable product