1. 9/5/2008EECS150 Lab Lecture #21 Designing with Verilog EECS150 Fall2008 - Lab Lecture #2 Chen Sun Adopted from slides designed by Greg Gibeling

2. 9/5/2008EECS150 Lab Lecture #22 Today Lab #1 Solution Top Down vs. Bottom Up Partitioning & Interfaces Behavioral vs. Structural Verilog Blocking vs. Non-Blocking Verilog Hardware Administrative Info Lab #2 Primitives

3. 9/5/2008EECS150 Lab Lecture #23 Lab #1 Solution (1) The Point Gets you experience with CAD tools Simulation Synthesis iMPACT Reinforces Timing Functional simulation isn’t enough Simulation != Synthesis Debugging differences are very difficult

4. 9/5/2008EECS150 Lab Lecture #24 Lab #1 Solution (2) Review: FPGA_TOP2.v FPGA Board High level instantiations Lab1Circuit.v The accumulator Two modules Unusual Lab1Testbench.v

5. 9/5/2008EECS150 Lab Lecture #25 Top Down vs. Bottom Up (1) Top Down Design Start by defining the project Then break it down Starts here:

6. 9/5/2008EECS150 Lab Lecture #26 Top Down vs. Bottom Up (2) Top Down Design Ends here:

7. 9/5/2008EECS150 Lab Lecture #27 Top Down vs. Bottom Up (3) Bottom Up Testing Faster, Easier and Cheaper Test each little component thoroughly Allows you to reuse components

8. 9/5/2008EECS150 Lab Lecture #28 Partitioning & Interfaces (1) Partitioning Break the large module up Decide what sub-modules make sense Partitioning is for your benefit It needs to make sense to you Each module should be: A reasonable size Independently testable Might be built by different people

9. 9/5/2008EECS150 Lab Lecture #29 Partitioning & Interfaces (2) Interfaces A concise definition of signals and timing Timing is vital, do NOT omit it Must be clean Don’t send useless signals across Bad partitioning might hinder this An interface is a contract Lets other people use/reuse your module

10. 9/5/2008EECS150 Lab Lecture #210 Behavioral vs. Structural (1) Rule of thumb: Behavioral doesn’t have sub-components Structural has sub-components: Instantiated Modules Instantiated Gates Instantiated Primitives Most modules are mixed Obviously this is the most flexible

11. 9/5/2008EECS150 Lab Lecture #211 Behavioral vs. Structural (2)

12. 9/5/2008EECS150 Lab Lecture #212 Behavioral vs. Structural (3)

13. 9/5/2008EECS150 Lab Lecture #213 Blocking vs. Non-Blocking (1) always @ (a) begin b = a; c = b; end always @ (posedge Clock) begin b <= a; c <= b; end C = B = A B = Old A C = Old B Verilog FragmentResult

14. 9/5/2008EECS150 Lab Lecture #214 Blocking vs. Non-Blocking (2) Use Non-Blocking for FlipFlop Inference posedge/negedge require Non-Blocking Else simulation and synthesis wont match Use ‘#1’ to show causality always @ (posedge Clock) begin b <= #1 a; c <= #1 b; end

15. 9/5/2008EECS150 Lab Lecture #215 Blocking vs. Non-Blocking (3) If you use blocking for FlipFlops: YOU WILL NOT GET WHAT YOU WANT! always @ (posedge Clock) begin b = a; // b will go away c = b; // c will be a FlipFlop end // b isn’t needed at all always @ (posedge Clock) begin c = b; // c will be a FlipFlop b = a; // b will be a FlipFlop end

16. 9/5/2008EECS150 Lab Lecture #216 Blocking vs. Non-Blocking (4) file xyz.v: module XYZ(A, B, Clock); inputB, Clock; outputA; regA; always @ (posedge Clock) A = B; endmodule file abc.v: module ABC(B, C, Clock); inputC, Clock; outputB; regB; always @ (posedge Clock) B = C; endmodule Race Conditions THIS IS WRONG!!

17. 9/5/2008EECS150 Lab Lecture #217 Blocking vs. Non-Blocking (5) file xyz.v: module XYZ(A, B, Clock); inputB, Clock; outputA; regA; always @ (posedge Clock) A <= B; endmodule file abc.v: module ABC(B, C, Clock); inputC, Clock; outputB; regB; always @ (posedge Clock) B <= C; endmodule Race Conditions THIS IS CORRECT!!

18. 9/5/2008EECS150 Lab Lecture #218 Verilog Hardware (1) assign Sum = A + B; reg [1:0]Sum; always @ (A or B) begin Sum = A + B; end

19. 9/5/2008EECS150 Lab Lecture #219 Verilog Hardware (2) assign Out = Select ? A : B; reg [1:0]Out; always @ (Select or A or B) begin if (Select) Out = A; else Out = B; end

20. 9/5/2008EECS150 Lab Lecture #220 Verilog Hardware (3) assign Out = Sub ? (A-B) : (A+B); reg [1:0]Out; always @ (Sub or A or B) begin if (Sub) Out = A - B; else Out = A + B; end

21. 9/5/2008EECS150 Lab Lecture #221 Verilog Hardware (4) reg [1:0]Out; always @ (posedge Clock) begin if (Reset) Out <= 2’b00; else Out <= In; end

22. 9/5/2008EECS150 Lab Lecture #222 Administrative Info Cardkeys Go to 253 Cory Will be activated on: September 15 th

23. 9/5/2008EECS150 Lab Lecture #223 Lab #2 (1) Lab2Top Accumulator Stores sum of all inputs Written in behavioral verilog Same function as Lab1Circuit Peak Detector Stores largest of all inputs Written in structural verilog

24. 9/5/2008EECS150 Lab Lecture #224 Lab #2 (2)

25. 9/5/2008EECS150 Lab Lecture #225 Lab #2 (3) Accumulator.v

26. 9/5/2008EECS150 Lab Lecture #226 Lab #2 (4) PeakDetector.v

27. 9/5/2008EECS150 Lab Lecture #227 Primitives (1) wireSIntermediate, SFinal, CPropagrate, CGenerate; xorxor1(SIntermediate,In,Out); andand1(CGenerate,In,Out); xorxor2(SFinal,SIntermediate,CIn); andand2(CPropagate,In,CIn); oror1(COut,CGenerate,CPropagate); FDCEFF(.Q(Out),.C(Clock),.CE(Enable),.CLR(Reset),.D(SFinal));

28. 9/5/2008EECS150 Lab Lecture #228 Primitives (2) wireSIntermediate, SFinal, CPropagrate, CGenerate; xorxor1(SIntermediate,In,Out); andand1(CGenerate,In,Out); xorxor2(SFinal,SIntermediate,CIn); andand2(CPropagate,In,CIn); oror1(COut,CGenerate,CPropagate); FDCEFF(.Q(Out),.C(Clock),.CE(Enable),.CLR(Reset),.D(SFinal));

29. 9/5/2008EECS150 Lab Lecture #229 Primitives (3) wireSIntermediate, SFinal, CPropagrate, CGenerate; xorxor1(SIntermediate,In,Out); andand1(CGenerate,In,Out); xorxor2(SFinal,SIntermediate,CIn); andand2(CPropagate,In,CIn); oror1(COut,CGenerate,CPropagate); FDCEFF(.Q(Out),.C(Clock),.CE(Enable),.CLR(Reset),.D(SFinal));