1. 15-447 Computer ArchitectureFall 2008 © September 17th, 2008 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f08/ CS-447– Computer Architecture M,W 2-3:50pm Lecture 10 Datapath & Control

2. 15-447 Computer ArchitectureFall 2008 © Lecture Objectives ° Learn what a datapath is, and how does it provide the required functions. ° Appreciate why different implementation strategies affects the clock rate and CPI of a machine. ° Understand how the ISA determines many aspects of the hardware implementation.

3. 15-447 Computer ArchitectureFall 2008 © The Big Picture of a Computer System DatapathControl Processor Main Memory Input / Output

4. 15-447 Computer ArchitectureFall 2008 © Focusing on CPU & Memory Register File ALU Datapath IR PC CPUMemory Data Address Control Unit

5. 15-447 Computer ArchitectureFall 2008 © The Datapath A load / store machine (RISC), register – register where access to memory is only done by load & store operations. Source 1 Register File ALU Source 2 Destination Result Control : (Register File)

6. 15-447 Computer ArchitectureFall 2008 © Register File Design # Bits / Register = 8=> 8 MUXs # Registers = 4=>4 to 1 each MUX 4->1 MUX control 4->1 MUX s1_buss2_bus Reg A Reg B Reg CReg D

7. 15-447 Computer ArchitectureFall 2008 © A0 A1 A2 A3C0 C1 C2 C3 MUX 4 -> 1 A0 B0 C0 D0 MUX 4 -> 1 A1 B1 C1 D1 MUX 4 -> 1 A2 B2 C2 D2 MUX 4 -> 1 A2 B2 C2 D2 B0 B1 B2 B3 MUX 4 -> 1 A0 B0 C0 D0 MUX 4 -> 1 A1 B1 C1 D1 MUX 4 -> 1 A2 B2 C2 D2 MUX 4 -> 1 A2 B2 C2 D2 D0 D1 D2 D3 S0 S1 S2 S3 s0 s1 s2 s3 Register File: 4 registers, 4 bits / register Control bits

8. 15-447 Computer ArchitectureFall 2008 © The Datapath The Result of the operation performed in the ALU needs to be stored in a register. Source 1 Register File ALU Source 2 Destination Result Control

9. 15-447 Computer ArchitectureFall 2008 © Destination: 2 registers / 3-bits per register DeMux3DeMux2DeMux1 Register 1Register 2 Control Result from ALU to Destination Bus

10. 15-447 Computer ArchitectureFall 2008 © Quiz °Draw your design of a register file: Three registers, each is 2-bits wide Two source buses, one destination bus °How many & what size: Muxes did you use? Demuxes did you use? °Total number of control lines?

11. 15-447 Computer ArchitectureFall 2008 © The Datapath A load / store machine (RISC), register – register where access to memory is only done by load & store operations. Source 1 Register File ALU Source 2 Destination Result Control : (ALU)

12. 15-447 Computer ArchitectureFall 2008 © Simple ALU Design control s1_bus dest_bus Add/Sub s2_bus Shift/Logic 16 to 8 MUX

13. 15-447 Computer ArchitectureFall 2008 © How about the Control? Register File ALU Datapath IR PC CPUMemory Data Address Control Unit

14. 15-447 Computer ArchitectureFall 2008 © The Control Unit Control Logic

15. 15-447 Computer ArchitectureFall 2008 © A simple device Build a custom controller for a vending machine. We could use a general purpose processor, but we might save money with a custom controller. Take coins, give drinks

16. 15-447 Computer ArchitectureFall 2008 © Input and Output Inputs: 10 drink selectors coin trigger refund button Outputs: 10 drink release latches Coin refund latch 10 pressure sensors

17. 15-447 Computer ArchitectureFall 2008 © Operation of Machine Accepts quarters only Once we get the money, they can select a drink. If they want a refund, release any coins inserted All drinks are $0.75 No free drinks! No stealing money!

18. 15-447 Computer ArchitectureFall 2008 © Building the controller °Finite State Remember how many coins have been put in the machine and what inputs are acceptable °Read-Only Memory (ROM) Define the outputs and state transitions °Custom combinational circuits Reduce the size (and therefore cost) of the controller

19. 15-447 Computer ArchitectureFall 2008 © Finite State Machines °A Finite State Machine (FSM) consists of: K states: S = {s 1, s 2, …,s k }, s 1 is initial state N inputs: I = {i 1, i 2, …,i n } M outputs: O = {o 1, o 2, …,o m } Transition function T(S,I) mapping each current state and input to next state Output Function P(S) [or P(S,I)] specifies output

20. 15-447 Computer ArchitectureFall 2008 © Two common state machines °Moore machine output function based on current state only °Mealy machine output function based on current state and current input see P&H page B-35

21. 15-447 Computer ArchitectureFall 2008 © FSM for vending machine 0 coins1 coin 3 coins2 coins Coin trigger Refund button Drink Select Ran out of specific drink selection

22. 15-447 Computer ArchitectureFall 2008 © FSM for addition in Load/Store Architecture Fetch Decode Store result ALU Execute Store result in R 1 Send signal to ALU to perform addition Fetch Instruction (Add R 1, R 2 ) Registers R 1 and R 2 Fetch next instruction

23. 15-447 Computer ArchitectureFall 2008 © D Q Implementing FSM D Q Current state Implement transition functions (using a ROM and combinational circuits) InputsOutputs Next state 2-bit state

24. 15-447 Computer ArchitectureFall 2008 © The Control Unit When Add is Exechting Control Logic

25. 15-447 Computer ArchitectureFall 2008 © The Control Unit When Add is Exechting Control Logic Instruction The control Turns on the required lines. In the Case of add, Ex: ALU OP, ALU source, Etc.

26. 15-447 Computer ArchitectureFall 2008 © ROMs and PROMs °Read Only Memory Array of memory values that are constant Non-volatile °Programmable Read Only Memory Array of memory values that can be written exactly once (destructive writes) °You can use ROMs to implement FSM transition functions ROM inputs: ROM address ; current state + primary inputs ROM outputs: ROM data ; next state + primary outputs