1. WinCupl Module M2.2 Section 4.2

2. Experiment 2

4. CUPL Header

5. CUPL Comments

6. CUPL Inputs and Outputs

7. CUPL Logic Equations

8. Running WinCupl

17. CUPL Chip Diagram in.DOC File

18. JEDEC File

19. JEDEC File Header

20. JEDEC File Fuse Map

21. Simulator Copy Exp2.pld to Exp2.si Delete everything after the header Add ORDER statement Add test VECTORS

22. Copy this header EXACTLY from the file exp2.pld and copy to the file exp2.si

23. Add the following to the file exp2.si ORDER statement Test vectors

24. ORDER Statement 01 HLLHHLHL Test Vector %2 means “leave 2 spaces when printing simulation results” Inputs: 0, 1 Outputs: L, H

25. Test Vectors The 4 test vectors represent the 4 rows in the truth table.

26. WinCupl Demo