1. EECC341 - Shaaban #1 Final Review Winter 2001 2-20-2002 Final Exam Review Combinational Logic Building Blocks: –Decoders, Encoders, Multiplexers, Demultiplexers –Implementing functions using decoders, multiplexers. Combinational Arithmetic Circuits: –Adders, Subtractors, Multipliers, Comparators, shifters. Sequential Logic Circuits: –Latches, Flip-Flips. Clocked Synchronous State Machines: –State Machine Analysis –State Machine Design Registers & Counters.

2. EECC341 - Shaaban #2 Final Review Winter 2001 2-20-2002 Binary n-to-2 n Decoders A binary decoder has n inputs and 2 n outputs. Only the output corresponding to the input value is equal to 1. : : n inputs n to 2 n decoder 2 n outputs

3. EECC341 - Shaaban #3 Final Review Winter 2001 2-20-2002 3-to-8 Binary Decoder F 1 = x'y'z xzy F 0 = x'y'z' F 2 = x'yz' F 3 = x'yz F 5 = xy'z F 4 = xy'z' F 6 = xyz' F 7 = xyz Truth Table: 3-to-8 Decoder X Y F0 F1 F2 F3 F4 F5 F6 F7 Z

4. EECC341 - Shaaban #4 Final Review Winter 2001 2-20-2002 Implementing Functions Using Decoders Any n-variable logic function, in canonical sum-of-minterms form can be implemented using a single n-to-2 n decoder to generate the minterms, and an OR gate to form the sum. –The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates. Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

5. EECC341 - Shaaban #5 Final Review Winter 2001 2-20-2002 Implementing Functions Using Decoders Example: Full adder S(x, y, z) =  (1,2,4,7) C(x, y, z) =  (3,5,6,7) 3-to-8 Decoder S2S1S0S2S1S0 x y z 0123456701234567 S C

6. EECC341 - Shaaban #6 Final Review Winter 2001 2-20-2002 Encoders If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2 n -to-n, priority encoders. The simplest encoder is a 2 n -to-n binary encoder, where it has only one of 2 n inputs = 1 and the output is the n-bit binary number corresponding to the active input. For an 8-to-3 binay encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are: Y0 = I1 + I3 + I5 + I7 Y1= I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 +I7............ 2 n inputs n outputs Binary encoder

7. EECC341 - Shaaban #7 Final Review Winter 2001 2-20-2002 8-to-3 Binary Encoder At any one time, only one input line has a value of 1. 00 00000100101 00000010110 00000001111 I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 Y 0 = I 1 + I 3 + I 5 + I 7 y 1 = I 2 + I 3 + I 6 + I 7 Y 2 = I 4 + I 5 + I 6 + I 7

8. EECC341 - Shaaban #8 Final Review Winter 2001 2-20-2002 Multiplexers A multiplexer (MUX) is a digital switches which connects data from one of n sources to the output. A number of select inputs determine which data source is connected to the output. Multiplexer b bits.... Data output n Data Sources s bits Select EnableEN SEL D0 D1 Dn-1 Y EN...... D0 D1 Dn-1...... 1Y 2Y bY SEL

9. EECC341 - Shaaban #9 Final Review Winter 2001 2-20-2002 4-to-1 MUX Truth table for a 4-to-1 multiplexer: muxY Inputs select S 1 S 0 I0I0 I1I1 I2I2 I3I3 4:1 MUX Y Inputs select S 1 S 0 I0I0 I1I1 I2I2 I3I3 01230123 Output

10. EECC341 - Shaaban #10 Final Review Winter 2001 2-20-2002 4-to-1 MUX Circuit S1S1 S0S0 0 1 2 3 2-to-4 Decoder I0I0 I1I1 I2I2 I3I3 Y S1S1 S0S0 I0I0 I1I1 I2I2 I3I3 Y

11. EECC341 - Shaaban #11 Final Review Winter 2001 2-20-2002 Larger Multiplexers Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be constructed from smaller multiplexers as shown: 4:1 MUX I0I1I2I3I0I1I2I3 S 1 S 0 4:1 MUX I4I5I6I7I4I5I6I7 S 1 S 0 2:1 MUX S2S2 Y

12. EECC341 - Shaaban #12 Final Review Winter 2001 2-20-2002 Larger Multiplexers A 16-to-1 multiplexer can be constructed from five 4-to-1 multiplexers:

13. EECC341 - Shaaban #13 Final Review Winter 2001 2-20-2002 Demultiplexers Digital switches to connect data from one input source to one of n outputs. Usually implemented by using n-to-2 n binary decoders where the decoder’s enable line is used for data input of the demultiplexer. 2X4 Decoder Select lines Input data (1bit) Enable One of four 1-bit outputs One of n Data Sources selected s bits Select b bits.... Data Input Demux One of n outputs 1-bit 4-output demultiplexer using a 2x4 binary decoder.

14. EECC341 - Shaaban #14 Final Review Winter 2001 2-20-2002 1-to-4 Demultiplexer demuxData D Outputs select S 1 S 0 Y 0 = D.S 1 '.S 0 ' Y 1 = D.S 1 '.S 0 Y 2 = D.S 1.S 0 ' Y 3 = D.S 1.S 0 2x4 Decoder D S1S0S1S0 Y 0 = D.S 1 '.S 0 ' Y 1 = D.S 1 '.S 0 Y 2 = D.S 1.S 0 ' Y 3 = D.S 1.S 0 E

15. EECC341 - Shaaban #15 Final Review Winter 2001 2-20-2002 Implementing n-variable Functions Using 2 n -to-1 Multiplexers Any n-variable logic function, in canonical sum-of- minterms form can be implemented using a single 2 n -to-1 multiplexer: –The n input variables are connected to the mux select lines. –For each mux data input line I i ( 0  i  2 n - 1): Connect 1 to mux input line I i if i is a minterm of the function. Otherwise, connect 0 to mux input line I i (because i is not a minterm of the function thus the selected input should be 0).

16. EECC341 - Shaaban #16 Final Review Winter 2001 2-20-2002 Example: 3-variable Function Using 8-to-1 mux Implement the function F(X,Y,Z) =  (1,3,5,6) using an 8-to-1 mux. –Connect the input variables X, Y, Z to mux select lines. –Mux data input lines 1, 3, 5, 6 that correspond to function minterms are connected to 1. –The remaining mux data input lines 0, 2, 4, 7 are connected to 0. mux X Y Z 0123456701234567 0101011001010110 F Mux Select Lines Mux Data Input Lines

17. EECC341 - Shaaban #17 Final Review Winter 2001 2-20-2002 Implementing n-variable Functions Using 2 n-1 -to-1 Multiplexers Any n-variable logic function can be implemented using a smaller 2 n-1 -to-1 multiplexer and a single inverter (e.g 4-to-1 mux to implement 3 variable functions) as follows: –Express function in canonical sum-of-minterms form. –Choose n-1 variables as inputs to mux select lines. –Construct the truth table for the function, but grouping inputs by selection line values (i.e select lines as most significant inputs). –Determine multiplexer input line i values by comparing the remaining input variable and the function F for the corresponding selection lines value i: Four possible mux input line i values: –Connect to 0 if the function is 0 for both values of remaining variable. –Connect to 1 if the function is 1 for both values of remaining variable. –Connect to remaining variable if function is equal to the remaining variable. –Connect to the inverted remaining variable if the function is equal to the remaining variable inverted.

18. EECC341 - Shaaban #18 Final Review Winter 2001 2-20-2002 Implement the function F(X,Y,Z) =  (0,1,3,6) using a single 4-to-1 mux and an inverter. –We choose the two most significant inputs X, Y as mux select lines. –Construct truth table: Example: 3-variable Function Using 4-to-1 mux mux X Y 01230123 1010 F Z We Determine multiplexer input line i values by comparing the remaining input variable Z and the function F for the corresponding selection lines value i: –when XY=00 the function F=1 (for both Z=0, Z=1) thus mux input0 = 1 –when XY=01 the function F=Z thus mux input1 = Z –when XY=10 the function F=0 (for both Z=0, Z=1) thus mux input2 = 0 –when XY=11 the function F=Z’ thus mux input3 = Z’ Mux Select Lines Mux Data Input Lines

19. EECC341 - Shaaban #19 Final Review Winter 2001 2-20-2002 Combinational Arithmetic Circuits Addition: –Half Adder (HA). –Full Adder (FA). –Carry Ripple Adders. –Carry Look-Ahead Adders. Subtraction: –Half Subtractor. –Full Subtractor. –Borrow Ripple Subtractors. –Subtraction using adders. Multiplication: –Combinational Array Multipliers.

20. EECC341 - Shaaban #20 Final Review Winter 2001 2-20-2002 Full Adder Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit. X00001111X00001111 Y00110011Y00110011 S01101001S01101001 C-out 0 1 0 1 C-in 0 1 0 1 0 1 0 1 Full Adder Truth Table S(X,Y, C-in) =  (1,2,4,7) C-out(x, y, C-in) =  (3,5,6,7) Inputs Outputs Sum S C-in X 0 10 1 00 01 11 10 Y C-in XY 0 1 2 3 6 7 4 5 1 1 1 1 C-in X 0 10 1 00 01 11 10 Y C-in XY 0 1 2 3 6 7 4 5 1 11 1 Carry C-out S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in) S = X  Y  (C-in) C-out = XY + X(C-in) + Y(C-in)

21. EECC341 - Shaaban #21 Final Review Winter 2001 2-20-2002 Full Adder Circuit Using AND-OR XY YC-in C-out XC-in X X Y C-in Y YY’ Y XX’ X C-in C-in’ C-in X’Y’C-in XY’C-in’ Sum S X’YC-in’ XYC-in X’ X X Y’ Y Y C-in Y C-in’ Full Adder XY S C-in C-out

22. EECC341 - Shaaban #22 Final Review Winter 2001 2-20-2002 n-bit Carry Ripple Adders An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders. –Each full adder represents a bit position j (from 0 to n-1). –Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. The output of a full adder at position j is given by: S j = X j  Y j  C j C j+1 = X j. Y j + X j. C j + Y. C j In the expression of the sum C j must be generated by the full adder at the lower position j-1. The propagation delay in each full adder to produce the carry is equal to two gate delays = 2  Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position, the total propagation delay of the adder is approximately: Total Propagation delay = 2 n 

23. EECC341 - Shaaban #23 Final Review Winter 2001 2-20-2002 Full Adder X1Y1 S1 C-in C-out Full Adder X0Y0 S0 C-in C-out C0 =0 Full Adder X2Y2 S2 C-in C-out Full Adder X3Y3 S3 C-in C-out C1 C2C3 C4 Data inputs to be added Sum output 4-bit Carry Ripple Adder Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0, C-out = C4 from the most significant position j=3 4-bit Adder X3X2X1X0 S3 S2 S1 S0 C-in C-out C4 Y3Y2Y1Y0 C0 =0 Inputs to be added Sum Output Total Propagation delay = 2 n  8   or 8 gate delays

24. EECC341 - Shaaban #24 Final Review Winter 2001 2-20-2002 Larger Adders Example: 16-bit adder using 4, 4-bit adders Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position. 4-bit Adder C-in C-out 4-bit Adder C-in C-out C0 =0 4-bit Adder C-in C-out 4-bit Adder C-in C-out C4 C8C12 C16 Data inputs to be added X (X0 to X15), Y (Y0-Y15) Sum output S (S0 to S15) Y3Y2Y1Y 0 X3X2X1X0 Y3Y2Y1Y 0 X3X2X1X0 Y3Y2Y1Y 0 X3X2X1X0 Y3Y2Y1Y 0 X3X2X1X0 S3 S2 S1 S0 Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x  2 n  x  8   or 32 gate delays

25. EECC341 - Shaaban #25 Final Review Winter 2001 2-20-2002 Carry Look-Ahead Adders The disadvantage of the ripple carry adder is that the propagation delay of adder (2 n  ) increases as the size of the adder, n is increased due to the carry ripple through all the full adders. Carry look-ahead adders use a different method to create the needed carry bits for each full adder with a lower constant delay equal to three gate delays. The carry out C-out from the full adder at position i or C j+1 is given by: C-out = C i+1 = X i. Y i + (X i + Y i ). C i By defining: –G i = X i. Y i as the carry generate function for position i (one gate delay) (If G i =1 C i+1 will be generated regardless of the value C i ) –P i = X i + Y i as the carry propagate function for position i (one gate delay) (If P i = 1 C i will be propagated to C i+1 ) By using the carry generate function G i and carry propagate function P i, then C i+1 can be written as: C- out = C i+1 = G i + P i. C i To eliminate carry ripple the term C i is recursively expanded and by multiplying out, we obtain a 2-level AND-OR expression for each C i+1

26. EECC341 - Shaaban #26 Final Review Winter 2001 2-20-2002 For a 4-bit carry look-ahead adder the expanded expressions for all carry bits are given by: C 1 = G 0 + P 0.C 0 C 2 = G 1 + P 1.C 1 = G 1 + P1.G 0 + P 1.P 0.C 0 C 3 = G 2 + P 2.G 1 + P 2.P 1.G 0 + P 2.P 1.P 0.C 0 C 4 = G 3 + P 3.G 2 + P 3.P 2.G 1 + P 3. P 2.P 1.G 0 + P 3.P 2.P 1.P 0.C 0 where G i = X i. Y i P i = X i + Y i The additional circuits needed to realize the expressions are usually referred to as the carry look-ahead logic. Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder. Carry Look-Ahead Adders

27. EECC341 - Shaaban #27 Final Review Winter 2001 2-20-2002 Carry Look-Ahead Circuit C i = G i-1 + P i-1. G i-2 + …. + P i-1.P i-2. …P 1. G 0 + P i-1.P i-2. …P 0. C 0

28. EECC341 - Shaaban #28 Final Review Winter 2001 2-20-2002 Binary Arithmetic Operations Subtraction Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed. Subtraction Example: 0 0 1 1 1 1 1 0 0 Borrow X 229 1 1 1 0 0 1 0 1 Y - 46 - 0 0 1 0 1 1 1 0 183 1 0 1 1 0 1 1 1

29. EECC341 - Shaaban #29 Final Review Winter 2001 2-20-2002 Full Subtractor Subtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit. This is called full subtraction. X00001111X00001111 Y00110011Y00110011 D01101001D01101001 B-out 0 1 0 1 B-in 0 1 0 1 0 1 0 1 Full Subtractor Truth Table S(X,Y, C-in) =  (1,2,4,7) C-out(x, y, C-in) =  (1,2,3,7) Inputs Outputs Difference D B-in X 0 10 1 00 01 11 10 Y B-in XY 0 1 2 3 6 7 4 5 1 1 1 1 B-in X 0 10 1 00 01 11 10 Y B-in XY 0 1 2 3 6 7 4 5 1 1 1 1 Borrow B-out S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in) S = X  Y  (C-in) B-out = X’Y + X’(B-in) + Y(B-in)

30. EECC341 - Shaaban #30 Final Review Winter 2001 2-20-2002 Full Subtractor Circuit Using AND-OR X’Y YB-in B-out X’B-in X’ Y B-in Y YY’ Y XX’ X B-in B-in’ B-in X’Y’B-in XY’B-in’ Difference D X’YB-in’ XYB-in X’ X X Y’ Y Y B-in Y B-in’ Full Subtractor XY D B-in B-out

31. EECC341 - Shaaban #31 Final Review Winter 2001 2-20-2002 An n-bit subtracor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways: By using n full subtractors and connecting them in series, creating a borrow ripple subtractor: –Each borrow out B-out from a full subtractor at position j is connected to the borrow in B-in of the full subtracor at the higher position j+1. By using an n-bit adder and n inverters: –Find two’s complement of Y by: Inverting all the bits of Y using the n inverters. Adding 1 by setting the carry in of the least significant position to 1 –The original subtraction (X - Y) now becomes an addition of X to two’s complement of Y using the n-bit adder. n-bit Subtractors

32. EECC341 - Shaaban #32 Final Review Winter 2001 2-20-2002 4-bit Borrow Ripple Subtractor Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0, B-out = B4 from the most significant position j=3 4-bit Subtractor X3X2X1X0 D3 D2 D1 D0 B-in B-out B4 Y3Y2Y1Y0 B0 =0 Inputs Difference Output D Full Subtractor X1Y1 D1 B-in B-out X0Y0 D0 B-in B-out B0 =0 X2Y2 D2 B-in B-out X3Y3 D3 B-in B-out B1 B2B3 B4 Data inputs to be subtracted Difference output D Full Subtractor Full Subtractor Full Subtractor

33. EECC341 - Shaaban #33 Final Review Winter 2001 2-20-2002 4-bit Subtractor Using 4-bit Adder 4-bit Adder X3 X2 X1 X0 D3 D2 D1 D0 C-in C-out C4 Y3 Y2 Y1 Y0 C0 = 1 Inputs to be subtracted Difference Output S3 S2 S1 S0

34. EECC341 - Shaaban #34 Final Review Winter 2001 2-20-2002 Binary Multiplication Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier. Ex. (unsigned) 11 1 0 1 1 multiplicand (4 bits) X 13 X 1 1 0 1 multiplier (4 bits) -------- ------------------- 33 1 0 1 1 11 0 0 0 0 ______ 1 0 1 1 143 1 0 1 1 --------------------- 1 0 0 0 1 1 1 1 Product (8 bits) An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n-bit adders where is adder is shifted by one position. For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits. X3 X2 X1 X0 x Y3 Y2 Y1 Y0 __________________________ X3.Y0 X2.Y0 X1.Y0 X0.Y0 X3.Y1 X2.Y1 X1.Y1 X0.Y1 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 _______________________________________________________________________________________________________________________________________________ P7 P6 P5 P4 P3 P2 P1 P0

35. EECC341 - Shaaban #35 Final Review Winter 2001 2-20-2002 4x4 Array Multiplier

36. EECC341 - Shaaban #36 Final Review Winter 2001 2-20-2002 Combinational Comparators Comparing two binary inputs A, B each n bits for equality (i.e A = B) is a common operation in computers. A single output combinational circuit to accomplish this can be constructed using n 2-input XNOR gates for bit-wise comparison plus one n-input AND gate. The output = 1 if A = B This can also be done by subtraction (A - B) and checking for a zero result using a single n-input NOR gate. Example: 1-bit comparator: A, B 1-bit each. –The 1-bit comparison requires a single XNOR gate Truth table: (A  B)’ ABAB 1-bit comparator Output

37. EECC341 - Shaaban #37 Final Review Winter 2001 2-20-2002 Example: 4-bit Comparator Comparator Output A3 B3 Compares A = A3 A2 A1 A0 with B = B3 B2 B1 B0 Output = 1 if A = B A2 B2 A1 B1 A0 B0

38. EECC341 - Shaaban #38 Final Review Winter 2001 2-20-2002 Combinational Shift Circuits An n-bit shift circuit (shifter) has a single n-bit data input A, and a single n-bit output R and a number of control inputs to determine the shift amount (0 to n-1). Possible shift operations include: – Shift left or right: Arithmetic right shift (the sign bit is shifted in), logic shift (0 is shifted in) Rotate left or right. Example: Original data input A = 11011 Shift left by one : 10110 Logic shift right by one: 01101 Arithmetic shift right by one: 11101 Rotate left by one: 10111 Combinational shift circuits are usually constructed using a number of levels of multiplexeres.

39. EECC341 - Shaaban #39 Final Review Winter 2001 2-20-2002 Example: Combinational 8-Bit Right Shifter 1 0 Mux select S A B D Basic Building Block 2-to-1 Mux 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S 2 S 1 S 0 A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7 Propagation delay: 2 gate delays per level x 3 levels = 6 gate delays How many Mux levels for 32-bit shifter? Propagation delay? S 2 S 1 S 0 shift amount from 0 to 7 Connect to: 0 for logic right shift or to A7 for arithmetic right shift or to A0 - A6 for rotate right { Three levels of Muxes used

40. EECC341 - Shaaban #40 Final Review Winter 2001 2-20-2002 Sequential Logic Circuits Combinational logic Memory elements Combinational outputs Memory outputs Inputs Sequential circuit = Combinational logic + Memory Elements Current State of A sequential Circuit: Value stored in memory elements (value of state variables). State transition: A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

41. EECC341 - Shaaban #41 Final Review Winter 2001 2-20-2002 Sequential Circuit Buliding Blocks: Generic Memory Elements A Memory Element: A logic device that can remember a single-bit value indefinitely, or change its value on command from its inputs. The output Q of the memory element represents the value stored in the memory element. This is also called the state variable of the memory elements. A memory element can be in one of two possible states: –Q = 0 (the memory element has 0 stored), also said be in state 0. –Q =1 (the memory element has 1 stored), also said to be in state 1. The commands to the memory element formed by its input(s) may include: –Set: Store 1 (Q=1) in the memory element. –Reset: Store 0 (Q=0) in the memory element. –Flip: Change stored value from 0 to 1 or from 1 to 0. –Hold value: Memory value does not change. Memory Element state transition: A change in the stored value from 0 to 1, or from 1 to 0 such as that caused by a flip command. command Memory element Memory Element Output: stored single-bit value Q

42. EECC341 - Shaaban #42 Final Review Winter 2001 2-20-2002 Sequential Circuit Memory Elements: Latches, Flip-Flops Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. Latches: –The output of a latch depends on its current inputs and on its previous inputs and its change of state can happen at any time when its inputs change. Flip-Flops: –The output of a flip-flop also depends on current and previous input but the change in output (change of state or state transition) occurs at specific times determined by a clock input.

43. EECC341 - Shaaban #43 Final Review Winter 2001 2-20-2002 Latches: –S-R Latch –S-R Latch With Enable –D-Latch Flip-Flops: –Edge-Triggered D Flip-Flop –Master/Slave S-R Flip-Flop –Master/Slave J-K Flip-Flop –Edge-Triggered J-K Flip-Flop –T Flip-Flop With Enable Sequential Circuit Memory Elements: Latches, Flip-Flops

44. EECC341 - Shaaban #44 Final Review Winter 2001 2-20-2002 S-R Latch An S-R (set-reset) latch can be built using two NOR- gates forming a feedback loop. The output of the S-R latch depends on current as well as previous inputs or state, and its state (value stored) can change as soon as its inputs change. R S Q QN S R Q QN 0 0 last Q Last QN 0 1 0 1 1 0 1 0 1 1 0 0 Function Table Circuit

45. EECC341 - Shaaban #45 Final Review Winter 2001 2-20-2002 S-R Latch With Enable Since the S-R latch is responsive to its inputs at all times an enable line C is used to disable or enable state transitions. Behaves similar to a regular S-R latch when enable C=1 Q QN S Enable C R S R C Q QN 0 0 1 last Q last QN 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 x x 0 last Q last QN Q Q S C R Function Table Circuit Logic Symbol

46. EECC341 - Shaaban #46 Final Review Winter 2001 2-20-2002 D-Latch Similar to S-R latch with an enable line, but both S, R are generated from one input D (data) and an inverter. Stores the value of its input D when enable C =1. C D Q QN 1 0 0 1 1 1 1 0 0 x Last Q Last QN Q QN D C Q Q D C Function Table Circuit Logic Symbol

47. EECC341 - Shaaban #47 Final Review Winter 2001 2-20-2002 Edge-Triggered D Flip-Flop Uses a pair of D latches and inverters. Similar in behavior to a D latch except that output and state changes happen at the rising or falling edge of an input clock. A D Flip-Flop triggered on the rising edge of the clock is given by: Q Q D CLK D CLK Q QN 0 0 1 1 1 0 x 0 Last Q Last QN x x Last Q Last QN Clock Q Q D C Q Q D C CLK D QM Master LatchSlave Latch Q QN Circuit Logic Symbol Function Table

48. EECC341 - Shaaban #48 Final Review Winter 2001 2-20-2002 Master/Slave S-R Flip-Flop S-R latches are substituted for the D latches in the negative-edge triggered D flip flop Q Q S C Q Q S C CLK S QM Master LatchSlave Latch Q QN RRR Q Q S C R S R C Q QN x x 0 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 undef. undef. Circuit Logic Symbol Function Table

49. EECC341 - Shaaban #49 Final Review Winter 2001 2-20-2002 Master/Slave J-K Flip-Flop Solves the problem when both S=R=1 When J=K=1 the last state is inverted. J K C Q QN x x 0 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q Q Q S C R Logic Symbol Function Table CLK Q Q S C Q Q S C J QM Master LatchSlave Latch Q QN K RR Circuit

50. EECC341 - Shaaban #50 Final Review Winter 2001 2-20-2002 Edge Triggered J-K Flip-Flop Created from an edge-triggered D flip-flop Q Q j CLK k J K C Q QN x x 0 last Q last QN x x 1 last Q last QN 0 0 last Q last QN 0 1 0 1 1 0 1 0 1 1 last QN last Q Function Table Logic Symbol Q Q D CLK Q QN J K CLK Circuit

51. EECC341 - Shaaban #51 Final Review Winter 2001 2-20-2002 T Flip-Flop With Enable Changes state on every clock cycle (rising edge of T). Q Q CLK D Q QN En T Q Q j CLK k EN Q QN T OR T En Q QN x 0 last Q last QN 1 last QN last Q Circuit Function Table

52. EECC341 - Shaaban #52 Final Review Winter 2001 2-20-2002 Clocked Synchronous State-Machines Such machines have the characteristics: –Sequential circuits designed using flip-flops. –All flip-flops use a common clock (clocked synchronous). –A machine using n flip-flops (state memory) has n state variables (the outputs of the flip-flops) and 2 n states. –In general, the next state and output of the machine both depend on the current state of the machine and on the current input: Next state = F(current state, input) output = G(current state, input) This type of state machine is called Mealy Machine –In some cases the next output depends only on the current state and not directly on the current input – Next state = F(current state, input) output = G(current state) Such machines are called Moore machines.

53. EECC341 - Shaaban #53 Final Review Winter 2001 2-20-2002 Clocked Synchronous State-Machine Model Next-state Logic F State Memory clock Output Logic G excitation current state outputs (Mealy machine) Moore Machine State memory: Usually edge-triggered D or JK flip-flops inputs clock

54. EECC341 - Shaaban #54 Final Review Winter 2001 2-20-2002 Device Characteristic Equations S-R latch Q* = S+R’.Q D latch Q* = D Edge-triggered D flip-flop Q* = D Master/Slave S-R flip-flop Q* = S+R’.Q Master/Slave J-K flip flop Q* = J.Q’ + K’.Q Edge Triggered J-K flip-flop Q* = J.Q’ + K’.Q T flip-flop Q* = Q’ T flip-flop with enable Q* = EN.Q’ + EN’.Q Latch/Flip-Flop Characteristic Equations

55. EECC341 - Shaaban #55 Final Review Winter 2001 2-20-2002 Clocked Synchronous State-machine Analysis Given the circuit diagram of a state machine: 1Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) –The input to each flip-flop is based upon current state and circuit inputs. 2Substitute excitation equations into flip-flop characteristic equations, giving transition equations: Q i * = H i ( D i ) 3From the circuit, find output equations: Z = G (Q, inputs) –The outputs are based upon the current state and possibly the inputs. 4Construct a state transition/output table from the transition and output equations: –Similar to truth table. –Present state on the left side. –Outputs and next state for each input value on the right side. –Provide meaningful names for the states in state table, if possible. 5Draw the state diagram which is the graphical representation of state table.

56. EECC341 - Shaaban #56 Final Review Winter 2001 2-20-2002 B 1 0, 1 A 01 B 1 / 1 0 / 1, 1 / 0 A 0 Moore Mealy State Diagram 0/0 Format: Arc = input X Node = state/output Q Format: Arc = input X / mealy output Y Node = state State Output Input Basic Format:

57. EECC341 - Shaaban #57 Final Review Winter 2001 2-20-2002 State Machine Analysis Example Q1 Q1' Q0 Q0' y x CP D Q Q' D Q Analyze the state machine: 1 Input (or excitation) equations: D0 = Q1’. X D1 = Q1. x + Q0. x 2 Characteristic equations: Q0* = D0 Q1* = D1 Find State equations: Q0* = Q1’. x Q1* = Q1. x + Q0. x 3 Output equation: y = (Q0 + Q1). x' This is a Mealy Machine since output = G(current state, input)

58. EECC341 - Shaaban #58 Final Review Winter 2001 2-20-2002 4 From the state equations and output equation, construct the state transition/output table: State Machine Analysis Example State equations: Q0* = Q1’. x Q1* = Q1. x + Q0. x Output equation: y = (Q0 + Q1). x' x Q1 Q0 0 1 0 0 00,001,0 0 100,111,0 1 000,110,0 1 100,110,0 Q1* Q0*, y Current State Next State when x =0 Output for current state when x =0 Next State when x =1 Output for current state when x =1 Input

59. EECC341 - Shaaban #59 Final Review Winter 2001 2-20-2002 5Draw the state diagram of the state machine. State Machine Analysis Example x Q1 Q0 0 1 0 0 00,001,0 0 100,111,0 1 000,110,0 1 100,110,0 Q1* Q0*, y 00 01 11 10 1/0 0/1 0/0 1/00/1 Arc = input x / output y Node = state state transition/output tablestate diagram

60. EECC341 - Shaaban #60 Final Review Winter 2001 2-20-2002 State Naming: –Optionally name the states and substitute state names S for state-variable combinations in transition/output table and in state diagram. –Example: For a circuit with two flip-flops: Q1 Q0 State Name 0 0 A 0 1 B 1 0 C 1 1 D Clocked State-machine Analysis: State Naming

61. EECC341 - Shaaban #61 Final Review Winter 2001 2-20-2002 Clocked State-machine Analysis Example: Transition/Output Table Using State Names x Q1 Q0 0 1 0 0 00,001,0 0 100,111,0 1 000,110,0 1 100,110,0 Q1* Q0*, y For the last example naming The States: Q1 Q0 State Name 0 0 A 0 1 B 1 0 C 1 1 D Transition/output Table: Transition/output Table using state names: x S 0 1 A A,0B,0 BA,1D,0 CA,1C,0 DA,1C,0 S*, y ABCDABCD

62. EECC341 - Shaaban #62 Final Review Winter 2001 2-20-2002 Clocked State-machine Analysis Example: State Diagram Using State Naming Naming The States: Q1 Q0 State Name 0 0 A 0 1 B 1 0 C 1 1 D 00 01 11 10 1/0 0/1 0/0 1/00/1 Arc = input x / output y Node = state State Diagram without state naming: State Diagram with state naming: A B D C 1/0 0/1 0/0 1/00/1

63. EECC341 - Shaaban #63 Final Review Winter 2001 2-20-2002 The timing diagram for a state machine graphically shows the state machine response in terms of state variables and output signals vs. time for given time-varying input signals and a given initial state. State machine timing diagrams can be generated using transition/output tables or state diagrams. Timing diagrams can be used to account for both combinational and flip-flop propagation delays. Example: For the state machine in the previous example show the timing diagram for the following input, assuming an initial state A and ignoring propagation delays: Clocked State-machine Analysis: State Machine Timing Diagram Clock 1 0 Input X Cycle: 0 1 2 3 4 5 6 7 1 0 Time

64. EECC341 - Shaaban #64 Final Review Winter 2001 2-20-2002 State Machine Timing Diagram Example Clock 1 0 Input X Cycle: 0 1 2 3 4 5 6 7 Q1 Q0 Output Y 1 0 A B D C A A B A 1 0 1 0 Time

65. EECC341 - Shaaban #65 Final Review Winter 2001 2-20-2002 State Machine Analysis Example 2 Analyze the state machine: D Q CLK Q D Q CLK Q D Q CLK Q X Y Q2’ Q0 Q1 CLK D0 D1 D2 Q0 Q1 Q2 Z1 Z2 State Memory Input Logic F Output Logic G Q2’

66. EECC341 - Shaaban #66 Final Review Winter 2001 2-20-2002 State Machine Analysis Example 2 Excitation Equations D0 = X. Y’.Q2 D1 = X. Q0 D2 = Y’ + Q1 State or Transition Equations Q0* = D0 = X. Y’. Q2’ Q1* = D1 = X. Q0 Q2* = D2 = Y’ + Q1 Characteristic Equations Q0* = D0 Q1* = D1 Q2* = D2 Output Equations Z1 = X. Q0 + Q1’ Z2= (Q1. Q2)’ 1 2 3

67. EECC341 - Shaaban #67 Final Review Winter 2001 2-20-2002 4 From the state equations and output equation, construct the state transition/output table: State Machine Analysis Example 2 state XY name Q2 Q1 Q0 00 01 11 10 A 0 0 0 100, 11 000, 11 000, 11 101, 11 B 0 0 1 100, 11 000, 11 010, 11 111, 11 C 0 1 0 100, 01 100, 01 100, 01 101, 01 D 0 1 1 100, 01 100, 01 110, 11 111, 11 E 1 0 0 100, 11 000, 11 000, 11 100, 11 F 1 0 1 100, 11 000, 11 010, 11 110, 11 G 1 1 0 100, 00 100, 00 100, 00 100, 00 H 1 1 1 100, 00 100, 00 110, 10 110,10 Q2* Q1* Q0*, Z1 Z2 (Next State, Outputs) Transition Equations Q0* = D0 = X. Y’. Q2’ Q1* = D1 = X. Q0 Q2* = D2 = Y’ + Q1 Output Equations Z1 = X. Q0 + Q1’ Z2= (Q1. Q2)’

68. EECC341 - Shaaban #68 Final Review Winter 2001 2-20-2002 State-machine Analysis Example 2: Transition/Output Table Using State Names XY S 00 01 11 10 A E, 11 A, 11 A, 11 F, 11 B E, 11 A, 11 C, 11 H, 11 C E, 01 E, 01 E, 01 F, 01 D E, 01 E, 01 G, 11 H, 11 E E, 11 A, 11 A, 11 E, 11 F E, 11 A, 11 C, 11 G, 11 G E, 00 E, 00 E, 00 E, 00 H E, 00 E, 00 G, 10 G,10 S*, Z1 Z2

69. EECC341 - Shaaban #69 Final Review Winter 2001 2-20-2002 State-machine Analysis Example 2: State Diagram (incomplete) A E C DH B F G Y (11) (11) X’ Y X Y (11) X’ Y’ (11) X Y’ (11) X’Y’ (11) XY’ (11) XY’ (01) X’+Y (01) XY’ (11) X’ (01) XY (11) Arc: input expression (outputs) = expression (Z1 /Z2)

70. EECC341 - Shaaban #70 Final Review Winter 2001 2-20-2002 State Machine Analysis Example 3 Analyze the state machine: J K CLK X Y Z Q1 Q2 J1 K1 J2 K2 J K Q Q Q Q

71. EECC341 - Shaaban #71 Final Review Winter 2001 2-20-2002 State Machine Analysis Example 3 Excitation Equations J1 = X K1 = X·Y J2 = X’ K2 = 0 Transition Equations Q1* = X·Q1’ + (X·Y)’ ·Q1 = X·Q1’ + X’·Q1 + Y’·Q1 Q2* = X’·Q2’ + 0’·Q2 = X’·Q2’ + Q2 Characteristic Equations Q*= J·Q’ + K’·Q Q1*= J1·Q1’ + K1’·Q1 Q2* = J2·Q2’ + K2’·Q2 Output Equation Z = X·Q1 + Q2 1 2 3

72. EECC341 - Shaaban #72 Final Review Winter 2001 2-20-2002 4 From the state equations and output equation, construct the state transition/output table: State Machine Analysis Example 3 XY S Q1 Q2 00011110 A 0 0 01,001,010,010,0 B 0 101,101,111,111,1 C 1 011,011,000,110,1 D 1 111,111,101,111,1 Q1* Q2*, Z Transition Equations Q1* = X·Q1’ + X’·Q1 + Y’·Q1 Q2* = X’·Q2’ + Q2 Output Equation Z = X·Q1 + Q2

73. EECC341 - Shaaban #73 Final Review Winter 2001 2-20-2002 State-machine Analysis Example 3: Transition/Output Table Using State Names XY S 00011110 A B,0B,0C,0C,0 BB,1B,1D,1D,1 CD,0D,0A,1C,1 DD,1D,1B,1D,1 S*, Z

74. EECC341 - Shaaban #74 Final Review Winter 2001 2-20-2002 State-machine Analysis Example 3: State Diagram AB C D 00,01,10 1 10 1 00,01 1 00,01 0 11 1 10,11 0 00,01 0 11 1 10,11 1 Arc Format: inputs xy output z

75. EECC341 - Shaaban #75 Final Review Winter 2001 2-20-2002 State Machine Design Procedure 1. Build state/output table (or state diagram) from word description using state names. 2. Minimize number of states (optional). 3. State Assignment: Choose state variables and assign bit combinations to named states. 4. Build transition/output table from state/output table (or state diagram) by substituting state variable combinations instead of state names. 5. Choose flip-flop type (D, J-K, etc.) 6. Build excitation table for flip-flop inputs from transition table. 7. Derive excitation equations from excitation table. 8. Derive output equations from transition/output table. 9. Draw logic diagram with excitation logic, output logic, and state memory elements.

76. EECC341 - Shaaban #76 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector Word description (110 input sequence detector): –Design a state machine with input A and output Y. –Y should be 1 whenever the sequence 1 1 0 has been detected on A on the last 3 consecutive rising clock edges (or ticks). –Otherwise, Y = 0 –Note: this is a Moore machine, that is the output, Y, depends only on inputs at previous clocks rising edges, not on the current input. Timing diagram interpretation of word description (only rising clock edges are shown): A CLK Y 0 1 1 0 0 1 1 1 0 1 1 1

77. EECC341 - Shaaban #77 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector Choosing States State Machine Design Example 1: 110 Detector Step1: Choosing States Possible states (What does the state machine need to remember?): –Initial: power up, no clocks yetY = 0 –No1s: first 1 not foundY = 0 –First1: first 1 foundY = 0 –Two1s: at least 2 consecutive 1s foundY = 0 –ALL: found 1 1 0 Y = 1 Are all the states needed? –Notice: Initial is equivalent to NO1s –We can drop the state Initial and replace it with state No1s

78. EECC341 - Shaaban #78 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector State Machine Design Example 1: 110 Detector Step 1: State/Output Table and Diagram S No1s First1 Two1s ALL A 0 No1s ALL No1s 1 First1 Two1s First1 Y0001Y0001 State Table S* NO1s 0 First1 0 Two1s 0 ALL 1 1 1 1 0 0 0 State Diagram Reset Format: Arc: input A Node: state/output Y 1 0

79. EECC341 - Shaaban #79 Final Review Winter 2001 2-20-2002 Step3: State Assignment Considerations Why does the choice of state assignment matter? –Has a big effect on the complexity of excitation and output equations and thus on the amount of combinational logic needed. How to find the best state assignment? –The only known way is to try all assignments and determine the resulting equations. N = 2: (2 2 )! = 4! = 24 assignments for 2 state bits N = 3: (2 3 )! = 8! = 40,320 assignments for three state bits. N = 4: (2 4 )! = 16! = 20,922,789,888,000 assignments for 4 state bits!!! THIS IS NOT PRACTICAL APPROACH!  Use heuristic guidelines for pretty good assignments. This is still an active area of research! There is no effective way to guarantee a “best” assignment. The heuristic methods sometimes perform poorly!

80. EECC341 - Shaaban #80 Final Review Winter 2001 2-20-2002 State Assignment Strategies Simplest Assignment: –Straight binary, not best; purely arbitrary assignment. One Hot Assignment: –Redundant encoding, each flip-flop is assigned a state. –Uses the same number of bits as there are states (not useful in large designs). –Simple to assign; simple next state logic (no state decoding required) –Output logic is simple! One OR gate per Moore output! Almost One Hot Assignment: –Almost same as One Hot, but one less state bit. –Use all 0’s to represent a state (usually INIT). –Must now decode state 0 if it is needed. Decomposed Assignment: –Use the “structure” of the state table to simplify next-state and output logic. –An “art” which requires much practice.

81. EECC341 - Shaaban #81 Final Review Winter 2001 2-20-2002 Example: State Assignment Strategies Alternative Assignments AB Q 1..Q 4 Q 1..Q 5 Q 1 Q 2 Q 3 Q 1 Q 2 Q 3 S 00 01 11 10 Z 0000 00001 000 000 INIT A0 A0 A1 A1 0 0001 00010 100 001 A0 OK0 OK0 A1 A1 0 0010 00100 101 010 A1 A0 A0 OK1 OK1 0 0100 01000 110 011 OK0 OK0 OK0 OK1 A1 1 1000 10000 111 100 OK1 A0 OK0 OK1 OK1 1 Almost One Decomposed Simplest One Hot Hot –Example decomposition: Initial State = all 0’s for easy RESET INIT state is different, so use Q 1 = 1 for non-INIT states; thus D1=1 Z = 1 in only 2 states, so use Q 2 =1 for states when Z = 1; thus  Z = Q 2 Use Q 3 = 1 for state transitions caused by A having the value of 1 (all destination states cause by A = 1, i.e. states A1 and OK1); thus D3=A THUS, simpler next state and output logic!

82. EECC341 - Shaaban #82 Final Review Winter 2001 2-20-2002 State Assignment Heuristic Guidelines Starting from the highest priority to the lowest: Choose initial coded state that’s easy to produce at reset: (all 0’s or 1’s) –This simplifies the initialization circuitry. Freely use any of the 2 n state codes for best assignment (i.e.. with s states, don’t just use the first s integers 0,1,…,s-1) Define specific bits or fields that have meaning with respect to input or output variables (decomposed codes). Consider using more than minimum number of state variables to allow for decomposed codes. Minimize number of state variables that change at each transition Simplify output logic.

83. EECC341 - Shaaban #83 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector State Machine Design Example 1: 110 Detector Step 3: State Assignment Choose state variable assignments: –Initial state all 0s –Q2 = last A, so Q2* = A –minimize number of transitions S No1s First1 Two1s ALL A 0 No1s ALL No1s 1 First1 Two1s First1 Y0001Y0001 S* Q1 Q2 0 0 0 1 1 1 1 0

84. EECC341 - Shaaban #84 Final Review Winter 2001 2-20-2002 Step 4: Build transition/output table from state/output table by substituting state variable combinations instead of state names. Step 5: Choose D Flip-Flops, so Q*= D Step 6: Excitation table: –Same as Transition/output table with Q1*=D1, Q2*=D2 State Machine Design Example 1: 110 Detector State Machine Design Example 1: 110 Detector Step 4: Transition/Output Table A 0 00 10 00 1 01 11 01 Y0001Y0001 Q1* Q2* =D1 D2 Step 6 Q1 Q2 0 0 0 1 1 1 1 0

85. EECC341 - Shaaban #85 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector State Machine Design Example 1: 110 Detector Steps 7, 8 : Excitation/Output Equations Step 7: Excitation equations: D1, D2 = F (A, Q1, Q2) Step 8: Output equation: Y = G (Q1, Q2) Y = Q1Q2’ (directly read from transition table) 0 0 1 0 0 1 1 0 Q1 Q2 A 000111 10 0 1 D1 : 0 0 1 1 Q1 Q2 A 000111 10 0 1 D2 : D1 = Q1Q2 + Q2A Q1Q2 Q2A D2 = A (as planned!)

86. EECC341 - Shaaban #86 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector Step 9: Logic Diagram D > Q Q D > Q Q A CLK RESET_L 1 1 Y P P C C Q1 Q2 D1 D2 P = Preset C = Clear Both active low CLK RESET_L reset to initial state (active low)

87. EECC341 - Shaaban #87 Final Review Winter 2001 2-20-2002 Word description (110/101 input sequence detector): –Design a state machine with input A and output Y. – Y = 1 when either sequence 1 1 0 or 1 0 1 has been detected on input A on the last 3 consecutive rising clock edges (or ticks). –Otherwise Y = 0 –Note: Correct sequences may overlap and still be accepted. Timing diagram interpretation of word description (only rising clock edges are shown): State Machine Design Example 2: 110/101 Detector A CLK y 0 1 0 1 0 1 1 0 1 0 0 0

88. EECC341 - Shaaban #88 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector Choosing States State Machine Design Example 2: 110/101 Detector Step1: Choosing States Possible states (What does the state machine need to remember?): –Idle: Initial state, no starting 1 yetY = 0 –Got1 : A = 1 on last tickY = 0 –Got10: Sequence A = 10 on last two ticksY = 0 –Got101: Sequence A = 101 on last three ticksY = 1 –Got11: Sequence A = 11 on last two ticksY = 0 –Got110: Sequence A = 110 on last three ticksY = 1 A CLK y Idle Got1 Got10 Got101 Got11 Got110 Got10 Got101 Got10 IDLE 0 1 0 1 0 1 1 0 1 0 0 0 Idle

89. EECC341 - Shaaban #89 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector State Machine Design Example 2: 110/101 Detector Step 1: State/Output Table S IDLE Got1 Got10 Got101 Got11 Got110 A 0 IDLE Got10 IDLE Got10 Got110 IDLE 1 Got1 Got11 Got101 Got11 Got101 Y000101Y000101 S*

90. EECC341 - Shaaban #90 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector State Machine Design Example 2: 110/101 Detector Step 1: State Diagram IDLE 0 Got1 0 Got10 0 Got101 1 Got11 0 Got110 1 0 0 1 0 0 0 0 1 1 1 1 1 Format: Arc: input A Node: state/output Y Reset

91. EECC341 - Shaaban #91 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector Steps 3: State Machine Design Example 2: 110/101 Detector Steps 3: State Assignment Step 3: Choose state variable assignments : –Initial state all 0s –Q1 = Y –Q3 = last A, so Q3* = A –minimum number of transitions S IDLE Got1 Got10 Got101 Got11 Got110 A 0 IDLE Got10 IDLE Got10 Got110 IDLE 1 Got1 Got11 Got101 Got11 Got101 Y000101Y000101 S* Q1 Q2 Q3 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 0 From Step 1:

92. EECC341 - Shaaban #92 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector Step 4: Transition/output table Step 5: Choose D Flip-flops Step 6: Excitation table –Same as Transition table A 0 000 010 000 010 110 000 ddd 1 001 011 111 011 111 ddd Y000101ddY000101dd Q1*Q2* Q3* =D1 D2 D3 Q1 Q2 Q3 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 0 1 0 0 1 0 1 Unused states?

93. EECC341 - Shaaban #93 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector State Machine Design Example 2: 110/101 Detector Steps 7: Excitation Equations Step 7: Excitation equations –D1, D2, D3 = F (A, Q1, Q2, Q3) d 1 1 d d 1 d Q1 Q2 Q3 A 000111 10 00 01 D1 : 11 10 d 1 1 1 d d Q1 Q2 Q3 A 000111 10 00 01 D3 : 11 10 d 1 1 d 1 1 1 d Q1 Q2 Q3 A 000111 10 00 01 D2 : 11 10 D1 = Q1’Q2Q3A’ + Q2Q3’A D2 = Q2A + Q3 D3 = A (as planned!)

94. EECC341 - Shaaban #94 Final Review Winter 2001 2-20-2002 State Machine Design Example 2: 110/101 Detector State Machine Design Example 2: 110/101 Detector Step 8: Output Equations Step 8: Output equation –Y = Q1 (as planned!) Step 9: Logic diagram –(3) D-Flip-flops + (3) 2-input gates + (1) 3-input AND gate + (1) 4-input AND gate –Draw the diagram. D1 = Q1’Q2Q3A’ + Q2Q3’A D2 = Q2A + Q3 D3 = A

95. EECC341 - Shaaban #95 Final Review Winter 2001 2-20-2002 State Machine Design Using J-K Flip-Flops State machine design step 6 ( building excitation table for flip-flop inputs from transition table): –When using D flip-flops, since the next state Q* = D, the excitation table is the same as the transition table with Q* replaced with D. –In the case of J-K flip-flops, the next state is given by: Q* = J. Q’ + K’. Q –In this case we cannot rearrange the characteristic equation to find separate equations for J, K. –Instead an application (or excitation) table for J-K flip-flops is used to obtain the corresponding values of J, K for a given Q to Q* transition: Q Q* J K 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0 J-K Flip-Flop Excitation Table

96. EECC341 - Shaaban #96 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector (Repeated Using J-K Flip-Flops) Word description (110 input sequence detector): –Design a state machine with input A and output Y. –Y should be 1 whenever the sequence 1 1 0 has been detected on A on the last 3 consecutive rising clock edges (or ticks). –Otherwise, Y = 0 Timing diagram interpretation of word description (only rising clock edges are shown): A CLK Y 0 1 1 0 0 1 1 1 0 1 1 1

97. EECC341 - Shaaban #97 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector State Machine Design Example 1: 110 Detector Step 1: State/Output Table and Diagram S No1s First1 Two1s ALL A 0 No1s ALL No1s 1 First1 Two1s First1 Y0001Y0001 State Table S* NO1s 0 First1 0 Two1s 0 ALL 1 1 1 1 0 0 0 State Diagram Reset Format: Arc: input A Node: state/output Y 1 0

98. EECC341 - Shaaban #98 Final Review Winter 2001 2-20-2002 Steps 1-4: No change. Step 5: Choose J-K Flip-Flops Step 6: Excitation table: Use J-K Flip-Flop Excitation Table. State Machine Design Example 1: 110 Detector State Machine Design Example 1: 110 Detector Using J-K Flip-flops Q1* Q2* A 0 00 10 00 1 01 11 01 Y0001Y0001 Q1 Q2 0 0 0 1 1 1 1 0 Q Q* J K 0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0 J-K Flip-Flop Excitation Table Transition Table (step 4): J1 K1, J2 K2 A 0 0d, 0d 0d, d1 d0, d1 d1, 0d 1 0d, 1d 1d, d0 d0, d0 d1, 1d Y0001Y0001 Q1 Q2 0 0 0 1 1 1 1 0 Excitation table (Step 6):

99. EECC341 - Shaaban #99 Final Review Winter 2001 2-20-2002 State Machine Design Example 1: 110 Detector Using J-K FF State Machine Design Example 1: 110 Detector Using J-K FF Steps 7, 8 : Excitation/Output Equations Step 7: Excitation equations: J1, K1, J2, K2 = F (A, Q1, Q2) Step 8: Output equation: Y = G (Q1, Q2) Y = Q1Q2’ (directly read from transition table) 0 0 d d 0 1 d d Q1 Q2 A 000111 10 0 1 J1 : J1 = Q2A d d 0 1 Q1 Q2 A 000111 10 0 1 K1 : K1 = Q2’ 0 d d 0 1 d d 1 Q1 Q2 A 000111 10 0 1 J2 : J2 = A d 1 1 d d 0 0 d Q1 Q2 A 000111 10 0 1 K2 : K2 = A’

100. EECC341 - Shaaban #100 Final Review Winter 2001 2-20-2002 Registers. Shift Registers: –Serial in, serial out shift register –Serial in, parallel out shift register –Parallel in, serial out shift register –Parallel in, parallel out shift register –Shift Register Applications Counters: –Ripple Counters –Synchronous Counters –Counter Applications Registers & Counters

101. EECC341 - Shaaban #101 Final Review Winter 2001 2-20-2002 Registers An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits. D 1Q CLR Q Q /1Q 1D D 2Q CLR Q Q /2Q 2D D 3Q CLR Q Q /3Q 3D D 4Q CLR Q Q /4Q 4D CLK /CLR 74LS175 Example: 74LS175 4-bit register CLK CLR 4Q 3Q 2Q 1Q 74LS175 1D 2D 3D 4D

102. EECC341 - Shaaban #102 Final Review Winter 2001 2-20-2002 Shift Registers Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle) –Shift Left is towards MSB 0 1 1 1 LSI Q3 Q2 Q1 Q0 1 1 1 LSI Q3 Q2 Q1 Q0 RSI 0 1 1 1 Q3 Q2 Q1 Q0 RSI 0 1 1 Q3 Q2 Q1 Q0 –Shift Right (or Shift Up) is towards MSB

103. EECC341 - Shaaban #103 Final Review Winter 2001 2-20-2002 Serial In, Serial Out Shift Register D Q CLK D Q CLK D Q CLK    SERIN CLOCK SEROUT For a n-bit SRG: Serial Out = Serial In delayed by n clock period 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 serout: - - - - 1 0 1 1 0 0 clock: SRG n > SI SO

104. EECC341 - Shaaban #104 Final Review Winter 2001 2-20-2002 Serial In, Parallel Out Shift register D Q CLK D Q CLK D Q CLK    SERIN CLOCK nQ 2Q 1Q Serial to Parallel Converter 4-bit shift register example: serin: 1 0 1 1 0 0 1 1 1 0 1Q: - 1 0 1 1 0 0 1 1 1 2Q: - - 1 0 1 1 0 0 1 1 3Q: - - - 1 0 1 1 0 0 1 4Q: - - - - 1 0 1 1 0 0 clock: SRG n > SI 1Q  2Q nQ (SO)

105. EECC341 - Shaaban #105 Final Review Winter 2001 2-20-2002 Parallel In, Serial Out Shift Register SERIN CLOCK D Q CLK D Q CLK D Q CLK    SEROUT    LOAD/SHIFT 1D 2D ND S L S L S L 1Q 2Q NQ Parallel to Serial Converter Load/Shift=1 D i Q i Load/Shift=0 Q i Q i +1

106. EECC341 - Shaaban #106 Final Review Winter 2001 2-20-2002 Parallel In, Parallel Out Shift Register SERIN CLOCK D Q CLK D Q CLK D Q CLK       LOAD/SHIFT 1D 2D ND 1Q 2Q NQ S L S L S L General Purpose: Makes any kind of (left) shift register

107. EECC341 - Shaaban #107 Final Review Winter 2001 2-20-2002 Shift Register Applications Example: 8-Bit Serial Adder... 7650 > x7x7 x6x6 x5x5 x0x0 7650 > y7y7 y6y6 y5y5 y0y0 7650 > FA Cout S Cin A B D Q CLK CLR CLK CLEAR_C z7z7 z6z6 z5z5 z0z0... CTL Sequential Implementation of: Z[7..0] = X[7..0] + Y[7..0] V

108. EECC341 - Shaaban #108 Final Review Winter 2001 2-20-2002 Counters Clocked sequential circuit with single-cycle state diagram –Modulo-m counter = divide-by-m counter –Most Common: n-bit binary counter, where m = 2 n Ù n flip-flops, counts 0 … 2 n -1 S3 S2 S1 Sm

109. EECC341 - Shaaban #109 Final Review Winter 2001 2-20-2002 Q Q T Q Q T Q Q T Q Q T CLK Q0 Q1 Q2 Q3 1 bit divide-by-2 2 bit divide-by-4 3 bit divide-by-8 4 bit divide-by-16 Uses Minimal Logic 4-bit Ripple Counter

110. EECC341 - Shaaban #110 Final Review Winter 2001 2-20-2002 Ripple Counter Problem n  T CQ for MSB change for n-bit ripple counter => minimum clk period CLK Q0 Q1 Q2 7 Should be 0 1 2 11 22 33

111. EECC341 - Shaaban #111 Final Review Winter 2001 2-20-2002 Synchronous Counters All clock inputs connected to common CLK signal –All flip-flop outputs change simultaneously t CQ after CLK ripple counters –Faster than ripple counters –More complex logic –Most frequently used type of counter

112. EECC341 - Shaaban #112 Final Review Winter 2001 2-20-2002 Synchronous Serial Counter Flip-flops enabled when all lower flip-flops = 1. Enable propagates serially — limits speed Requires (n-1)  t < T CLK All outputs change simultaneously t CQ after CLK >T Q EN CLK CNTENQ0 Q1 Q2 Q3 Q EN >T Q EN >T Q EN >T  t

113. EECC341 - Shaaban #113 Final Review Winter 2001 2-20-2002 Synchronous Parallel Counter Single-level enable logic per flip-flop Fastest and most complex type of counter Requires  t < T CLK All outputs change simultaneously t CQ after CLK >T Q EN >T Q EN >T Q EN >T Q EN CLK CNTENQ0 Q1 Q2 Q3