1. Workload distribution in satellites Performed by : Maslovsky Eugene Grossman Vadim Instructor:Rivkin Inna Spring 2004 המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Workload distribution between with a PPC405 hardcore CPU and a Microblaze softcore CPU. The Microblaze will operate as an I/O dedicated CPU, relieving the "main" CPU from the need to constantly handle I/O. The project is going to be implemented on the Virtex-II Pro FPGA.

3. Concept Before Main CPU I/O per. Before : Main CPU deals with ALL the I/O ALL the time After EV04S (I/O CPU) Main CPU I/O per. After : Main CPU deals ONLY with the device ONLY when needed המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

4. System Description MicroBlaze I/O CPU An intermediate buffers unit – Asynchronous FIFOs – System Controller – Interrupt generating configurable controller – Empty indicator controller A buffers unit is assigned for one peripheral, or for several, using a simple communication protocol המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

5. Specifications Hardware – ML-310 board with PPC405 CPU – MicroBlaze soft core CPU – Controllers written in VHDL Software – Testing Code for the CPUs – Drivers for the logic המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

6. The main CPUAux. I/O CPU Our “module” BUS System block diagram Input devices Output devices BUSes I/O Ports BUS X The CPUs cannot talk with each other המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory

7. FPGA Architecture diagram DLMB PPC MB I/O #1I/O #2I/O #3 OPB PLB Bram + Controller PLB2OPB ILMB Bram + Controller EV04S EV04S MB IntcPPC Intc EV04S המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory