1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 15 - ASIC Design with Verilog Spring 2007

2. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog2 Announcements  Reading  Book: 4.1-4.8, 5.1-5.2  Verilog Handout: 5.1-5.3, 5.6

3. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog3 Where we are  Last Time:  Logical Effort  Testing  Today:  ASIC Design with Verilog Overview Verilog Review - Combinational Design

4. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog4 ASIC Design with Logic Synthesis  Goal: automate ASIC Design Process  Translate HDL into Boolean Expressions  Optimize design for cost and timing constraints  Map into ASIC gate library  History  Two-level logic optimization algorithms - early 1980s  Multi-level logic optimization - mid-1980s  Commercial logic synthesis (Synopsys) - late 1980s  Tighter integration with physical design - present

5. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog5 Logic Optimization  Two-Level Logic Optimization  Minimize logic in AND/OR form  Simple Optimization: Karnaugh Map  Computer-Based Optimization Quine/McCluskey - Exact method (slow) Espresso - Heuristic method (fast)  Multi-Level Logic Optimization  Factor common subexpressions in a logic network  Simplify individual nodes using two-level optimization  Apply multiple transformations with command scripts  Integrate with timing analysis, technology mapping

6. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog6 Outline - Introduction to Verilog  Goals of HDL-Based Design  Verilog Background  A First Example  Module and Port Declarations  Modeling with Continuous Assignments  Some Language Details  Modeling with Hierarchy  Modeling with always blocks (combinational logic)  Demonstration: Using Verilogger  Discuss Project 1  Summary

7. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog7 HDL Overview  What is an HDL? A language for  simulation - “event driven” model of execution  synthesis - generates designs that match simulated behavior for a subset of the language  Common HDLs:  Verilog HDL  VHDL - VHSIC (Very High-Speed IC) HDL  SystemC - C++ with class libraries to support System-Level Design and Hardware Design

8. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog8 Verilog Simulators  On Windows Machines:  Synapticad Verilogger  Mentor ModelSim  On the Linux (?): Synopsys vcs  vcs -RI

9. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog9 Verilog module construct  Key building block of language  declaration - specifies a module interface Input & output ports connections to outside world “black box” model - no details about internals  body - specifies contents of "black box" behavior - what it does structure - how it's built from other "black boxes"

10. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog10 A First Example  Full Adder: module fulladder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = a & b | a & cin | b & cin; endmodule Ports Port Declarations Semicolon NO Semicolon Continuous Assignment Statements

11. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog11 Comments about the First Example  Verilog describes a circuit as a set of modules  Each module has input and output ports  Single bit  Multiple bit - array syntax  Each port can take on a digital value (0, 1, X, Z) during simulation  Three main ways to specify module internals  Continuous assignment statements - assign  Concurrent statements - always  Submodule instantiation (hierarchy)

12. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog12 Bitwise Operators  Basic bitwise operators: identical to C/C++/Java module inv(a, y); input[3:0]a; output [3:0]y; assign y = ~a; endmodule Unary Operator: NOT 4-bit Ports

13. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog13 Reduction Operators  Apply a single logic function to multiple-bit inputs module and8(a, y); input[7:0]a; output y; assign y = &a; endmodule Reduction Operator: AND

14. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog14 Conditional Operators  Like C/C++/Java Conditional Operator module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; // if s=1, y=d1, else y=d0 endmodule Comment

15. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog15 More Operators  Equivalent to C/C++/Java Operators  Arithmetic: + - * / &  Comparison: == != >=  Shifting: >  Example: module adder(a, b, y); input[31:0]a, b; output[31:0]y; assign y = a + b; endmodule  Small expressions can create big hardware!

16. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog16 Bit Manipulation: Concatenation  { } is the concatenation operator module adder(a, b, y, cout); input[31:0]a, b; output[31:0]y; output cout; assign {cout,y} = a + b; endmodule Concatenation (33 bits)

17. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog17 Bit Manipulation: Replication  { n {pattern} } replicates a pattern n times module signextend(a, y); input[15:0]a; output [31:0]y; assign y = {16{a[15]}, a[15:0]}; endmodule Copies sign bit 16 times Lower 16 Bits

18. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog18 Internal Signals  Declared using the wire keyword module fulladder(a, b, cin, s, cout); inputa, b, cin; output s, cout; wireprop, gen; assign prop = a ^ b; assign gen = a | b; assign s = prop ^ cin; assign cout = gen | (cin & prop); endmodule

19. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog19 Some Language Details  Syntax - See Quick Reference Card  Major elements of language:  Lexical Elements (“tokens” and “token separators”)  Data Types and Values  Operators and Precedence  Syntax of module declarations

20. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog20 Verilog Lexical Elements  Whitespace - ignored except as token separators  blank spaces  tabs  newlines  Comments  Single-line comments //  Multi-line comments /* … */  Operators- unary, binary, ternary  Unary a = ~b;  Binary a = b && c;  Ternary a = (b < c) ? b : c;

21. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog21 Verilog Numbers  Sized numbers: '  - decimal number specifying number of bits  - base of number decimal 'd or 'D hex 'h or 'H binary ‘b or ‘B  - consecutive digits normal digits 0, 1, …, 9 (if appropriate for base) hex digitsa, b, c, d, e, f x "unknown" digit z "high-impedance" digit  Examples 4’b111112’h7af16’d255

22. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog22 Verilog Numbers (cont'd)  Unsized numbers  Decimal numbers appearing as constants (236, 5, 15, etc.)  Bitwidth is simulator-dependent (usually 32 bits)  Negative numbers  sized numbers: '-' before size -8'd127 -3'b111  unsized numbers: '-' before first digit -233  Underline '_' can be used as a "spacer 12'b00010_1010_011 is same as 12'b000101010011

23. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog23 Verilog Strings  Anything in quotes is a string: "This is a string" "a / b"  Strings must be on a single line  Treated as a sequence of 1-byte ASCII values  Special characters - C-like (\)

24. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog24 Verilog Identifiers  Starting character: alphabetic or '_'  Following characters: alpha, numeric, or '_'  Examples: george_paul  "Escaped" identifiers:  start with backslash  follow with any non-whitespace ASCII  end with whitespace character  Examples: \212net\**xyzzy**\$foo  Special notes:  Identifiers are case sensitive  Identifiers may not be reserved words

25. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog25 Verilog Reserved Words alwaysandassignbeginbufbufif0bufif1 case casexcasezcmos deassigndefaultdefparamdisableedge elseendendcaseendfunctionendmodule endprimitiveendspecifyendtableendtaskeventfor forceforeverforkfunctionhighz0highz1ififnone initialinoutinputintegerjoinlargemacromodule mediummodulenandnegedgenmosnor not notif0notiforoutputparameterpmos posedgeprimitivepull0pull1pulldownpulluprcmos realrealtimeregreleaserepeatrnmosrpmosrtran rtranif0rtranif1scalaredsmallspecifyspecparamstrong0 strong1supply0supply1tabletasktimetrantranif0 tranif1tritri0tri1triandtriortriregvectored waitwandweak0weak1whilewireworxnor xor

26. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog26 Verilog Data Types  Nets - connections between modules  input, output ports  wires - internal signals  Other types: wand, wor, trior, trireg (ignore for now)  Advanced Data Types (more later)  Vectors - multiple bit wires, registers, etc.  reg - Variables that are assigned values  Arrays and Memories  Parameters

27. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog27 Operators and Precedence  Override with parentheses () when needed

28. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog28 Verilog Module Declaration  Describes the external interface of a single module  Name  Ports - inputs and outputs  General Syntax: module modulename ( port1, port2,... ); port1 direction declaration; port2 direction declaration; reg declarations; module body - “parallel” statements endmodule // note no semicolon (;) here!

29. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog29 Verilog Body Declaration - “Parallel” Statements  Parallel statements describe concurrent behavior (i.e., statements which “execute” in parallel)  Types of Parallel Statements:  assign - used to specify simple combinational logic  always - used to specify repeating behavior for combinational or sequential logic  initial - used to specify startup behavior (not supported in synthesis, but often used in simulation)  module instantiation - used for structure  … and other features we’ll talk about later

30. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog30 Combinational Modeling with always  Motivation  assign statements are fine for simple functions  More complex functions require procedural modeling  Basic syntax: always (sensitivity-list) statement or always (sensitivity-list) begin statement-sequence end Signal list - change activates block Sequential statement ( =, if/else, etc.) Compound Statement - sequence of sequential statements

31. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog31 Sequential Statements  Similar to statements in C, Java, etc.  Like C/Java, statements execute sequentially  Value assigned values must be declared as “ reg ”  When combined with always block  Code is “activated” when inputs change  Full execution determines final value  Storage implied if values not assigned for all conditions

32. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog32 Combinational Modeling with always  Example: 4-input mux behavioral model module mux4(d0, d1, d2, d3, s, y); input d0, d1, d2, d3; input [1:0] s; output y; reg y; always @(d0 or d1 or d2 or d3 or s) case (s) 2'd0 : y = d0; 2'd1 : y = d1; 2'd2 : y = d2; 2'd3 : y = d3; default : y = 1'bx; endcase endmodule Blocking assignments (immediate update)

33. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog33 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module  Original mux2 module: module mux2(d0, d1, s, y); input[3:0]d0, d1; inputs; output [3:0]y; assign y = s ? d1 : d0; endmodule

34. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog34 Modeling with Hierarchy  Create instances of submodules  Example: Create a 4-input Mux using mux2 module module mux4(d0, d1, d2, d3, s, y); input[3:0]d0, d1, d2, d3; input[1:0]s; output [3:0]y; wire[3:0]low, high; mux2 lowmux(d0, d1, s[0], low); mux2 highmux(d2, d3, s[0], high); mux2 finalmux(low, high, s[1], y); endmodule Instance NamesConnections

35. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog35 Larger Hierarchy Example  Use full adder to create an n-bit adder module add8(a, b, sum, cout); input [7:0] a, b; output [7:0] sum; output cout; wire [7:0] c; // used for carry connections assign c[0]=0; fulladder f0(a[0], b[0], c[0], sum[0], c[1]); fulladder f1(a[1], b[1], c[1], sum[1], c[2]); fulladder f2(a[2], b[2], c[2], sum[2], c[3]); fulladder f3(a[3], b[3], c[3], sum[3], c[4]); fulladder f4(a[4], b[4], c[4], sum[4], c[5]); fulladder f5(a[5], b[5], c[5], sum[5], c[6]); fulladder f6(a[6], b[6], c[6], sum[6], c[7]); fulladder f7(a[7], b[7], c[7], sum[7], cout); endmodule

36. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog36 Hierarchical Design with Gate Primitives  “Built-In” standard logic gates and or not xor nand nor xnor  Using Gate Primitives: and g1(y, a, b, c, d);  How are the different from operators ( &, |, ~, etc.)?  Operators specify function  Gate primitives specify structure Output Inputs (variable number)

37. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog37 Gate Primitives Example  2-1 Multiplexer module mux2s(d0, d1, s, y); wire sbar, y0, y1; not inv1(sbar, s); and and1(y0, d0, sbar); and and2(y1, d1, s); or or1(y, y0, y1); endmodule;  Why shouldn’t we use gate primitives?  Requires “low-level” implementation decisions  It’s usually better to let synthesis tools make these

38. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog38 Lab 8 - Comb. Design with Verilog  Prelab: write out case statement by hand for binary decoder  In the lab:  Type in and simulate binary decoder using Verilogger  FTP to Linux & synthesize using Synopsys tools  FTP to Suns & convert optimized logic to layout

39. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog39 Lab 8 - Decoder Design in Verilog  Part 1: design, simulate, and synthesize a decoder module dec2_4(d_in, d_out); input [1:0] d_in; output [3:0] d_out; reg [3:0] d_out; always @(d_in) begin case (d_in) 2’b00 : d_out = 4’b0001; … default: d_out = 4’bxxxx; endcase end endmodule d_in d_out Fill in the 4 cases with the proper values

40. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog40 Lab 8 - Decoder Design in Verilog  Part 2: add an inverted output to your decoder module dec2_4(d_in, d_out, d_out_b); input [1:0] d_in; output [3:0] d_out, d_out_b; reg [3:0] d_out, d_out_b; always @(d_in) begin case (d_in) 2’b00 : d_out = 4’b0001; … default: d_out = 4’bxxxx; endcase end endmodule Add code to generate d_out_b d_in d_out d_out_b

41. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog41 Lab 8 - Additional Tasks  Modify decoder to intentionally create a “latch inference” and synthesize  Create, simulate, and synthesize designs for:  Row decoder for D/A converter (include d2 input)  4-bit incrementer  4-bit adder

42. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog42 Lab 8 - CAD Tools  Verilogger - simulator  Synopsys - synthesis  db2mag - placement/routing  magic - use to view resulting layout

43. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog43 Synthesis Example: mux4 module mux4(d0, d1, d2, d3, s, y); input d0, d1, d2, d3; input [1:0] s; output y; reg y; always @(d0 or d1 or d2 or d3 or s) case (s) 2'd0 : y = d0; 2'd1 : y = d1; 2'd2 : y = d2; 2'd3 : y = d3; default : y = 1'bx; endcase endmodule

44. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog44 mux4 - Before Optimization

45. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog45 mux4 - After Optimization

46. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog46 mux4 - Layout

47. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog47 More about always  Specifies logic with procedural statements  Simulation model: executes statements in order  Synthesized hardware: matches simulation  “ reg ” declarations  treat like variables in C or Java  assignment: holds value until a new assignment is made module my_logic(a, b, c, d); input a, b; output c, d; reg c,d; always @(a or b) begin c = a & b; d = b ^ c; end endmodule

48. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog48 Synthesizing Comb. Logic  When no if, case, or loop statements:  Assignment statements generate logic  Outputs are values of last assignments  Logic optimized, reduced during synthesis module my_logic(a, b, c, d); input a, b; output c, d; reg c,d; always @(a or b) begin c = a & b; d = b ^ c; c = d | a; end endmodule

49. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog49 Synthesizing Comb. Logic - if/else  if/else statements become multiplexers  multiplexers follow statement order always @(c or d or x or y) begin if (c == 1’b1) z = x + y; else z = x - y; if (d == 1’b0) w = z; else w = x; end

50. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog50 Synthesizing Comb. Logic - if /else if / else  Each else implies mutual exclusion  if / else if / else creates a priority encoder always @(c or d or x or y) begin if (c == 1’b1) z = x + y; else if (d == 0’b0) z = x - y; else z = x; end  Use sequential if statements without else if to avoid priority if desired

51. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog51 Synthesizing Comb. Logic - if without else  if without else : output depends on previous value always @(a or x or y) begin w = x + y; if (a == 1’b1) w = x; end  What if no previous value is specified?  Must preserve the semantics of the language  This requires a latch inference

52. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog52 Synthesizing Comb. Logic - if without else (latch inference)  if without else : output depends on previous value always @(a or x or y) begin if (a == 1’b1) w = x; end  What if no previous value is specified?  Must preserve the semantics of the language  This requires a latch inference to store “old” value

53. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog53 Synthesizing Comb. Logic - case statements  Verilog case : treated as if / else if / else... always @(e or x or y) begin case (e) 2’b00 : w = x + y; 2’b01 : w = x - y; 2’b10 : w = x & y; default: w = 4’b0000; endcase end  Use default to avoid latch inference!  To avoid priority: use parallel_case “pragma” case (e) //synopsys parallel_case 2’b00 : w = x + y;... end

54. ECE 425 Spring 2007Lecture 15 - Design w/ Verilog54 Coming Up  Sequential Logic  Latches  Flip-Flops  Finite State Machines