1. 1 COMP541 Interrupts, DMA, Serial I/O Montek Singh April 24, 2007

2. 2Interrupts  Two main kinds  Internal Error when executing an instruction Error when executing an instruction  Floating point exception  Trying to access protected memory System call System call  To request OS services  External I/O I/O

3. 3Internal  More complicated because may abort instruction  Or OS could correct the situation  Example: Access to protected memory not allowed

4. 4 When Interrupt Occurs  Interrupt enable register Sometimes levels of interrupts individually enabled/disabled Sometimes levels of interrupts individually enabled/disabled  PC is changed to new location One or more interrupt locations stored One or more interrupt locations stored Or a fixed location Or a fixed location  Old PC saved to register or stack Many machines have stack pointer Many machines have stack pointer

5. 5Registers  Sometimes registers saved by hardware Some machines have one or more sets of registers Some machines have one or more sets of registers  On other architectures software must save registers  Sometimes instruction to return from interrupt Otherwise, use the procedure return instruction, RET Otherwise, use the procedure return instruction, RET

6. 6 Cause of Interrupt  Need way to determine what caused interrupt Note it can be more than one thing Note it can be more than one thing  Vectored Interrupts Different types cause branches to different locations Different types cause branches to different locations Sometimes prioritized Sometimes prioritized  Register to store cause

7. 7 Supervisory Mode  Modern computers have user mode and one or more supervisory modes  User mode restricted Can’t write to many system registers, such as interrupt enable Can’t write to many system registers, such as interrupt enable Can’t write to some parts of memory Can’t write to some parts of memory Usually I/O restricted Usually I/O restricted  Interrupts cause switch to supervisory mode Question: Which interrupts? Question: Which interrupts?

8. 8 Some Interrupt Hardware  Interrupts ORed  Response if IE and at end of instruction  Ack interrupt  Vector address to PC  PC to stack

9. 9 Potential Microcode SP  SP – 1 M[SP]  PC SP  SP – 1 M[SP]  PSR PSR is processor status register PSR is processor status register EI  0 INTACK  1 PC  IVAD

10. 10 Return Similar  Very similar to return from procedure  PSR holds IE bit  Restoring PSR turns interrupts on

11. 11 Restarting Instruction?  Imagine the interrupt (exception) was a page fault  Need to get the page, and then rerun the instruction  Easy instructions help out  Otherwise may need to save some intermediate state Imagine block-move instruction Imagine block-move instruction

12. 12 Direct Memory Access (DMA)  Programmed I/O is when CPU reads/writes every word Problem: overhead is high; nothing else getting done on CPU Problem: overhead is high; nothing else getting done on CPU Especially for mass-storage devices like disk Especially for mass-storage devices like disk  DMA: Let device controller read/write directly to memory Challenges? Challenges?

13. 13Procedure  DMA device takes over main bus  Becomes bus master  Asserts addresses  Basically interfaces to memory or memory controller

14. 14How?  DMA device requests bus (assert BR)  CPU grants request (assert BG)  CPU takes its signals to Hi-Z

15. 15Transfers  Continuous – DMA controller transfers all data (say a disk sector) at once As many memory cycles as data As many memory cycles as data  Burst – DMA controller cycle steals, takes a cycle at end of every CPU instruction  Note that now the chip that controls memory (northbridge), not CPU, is likely to do this

16. 16 End of DMA  Controller needs to inform CPU  De-assert BR  Then CPU lowers BG and proceeds

17. 17 DMA Controller  Needs typical I/O signals Interrupt request Interrupt request Status of device Status of device  Also needs controls for DMA transfer Memory address Memory address Word count Word count

18. 18 Block Diagram

19. 19 Typical Driver Interface  Set the memory address  Set word count  Assert GO (usually bit in control word)  DMA controller requests interrupt when transfer complete

20. 20RS-232  “Asynchronous”  Both sides have precise clocks  Agree on speed  Receiver syncs during start bit

21. 21USB  One master The PC The PC  Idea was to have thin cables and plug and play

22. 22 USB – Packet serial I/O  Four wires total  +5v and GND  Two signal wires Twisted pair Twisted pair Differential signaling Differential signaling Differential 1 is D+ > 2.8v and D- 2.8v and D- < 0.3v Differential 0 is opposite Differential 0 is opposite Also a single-ended zero when D+ & D- low (end of packet, reset, disconnect) Also a single-ended zero when D+ & D- low (end of packet, reset, disconnect)

23. 23Speed  Three speeds High is 480 Mb/s High is 480 Mb/s Full is 12 Mb/s Full is 12 Mb/s Low is 1.5 Mb/s Low is 1.5 Mb/s  Pull-up indicates full/low  High speed starts as full, then handshakes and transitions  High and low speeds interpret zeros and ones inverted.

24. 24Coding  NRZI  Bit stuffing Since a string of 1s causes no transitions, synchronization may be lost Since a string of 1s causes no transitions, synchronization may be lost A zero is stuffed in after six consecutive ones A zero is stuffed in after six consecutive ones  Sync field Each packet starts with a sync Each packet starts with a sync 8 bits: 00000001 8 bits: 00000001

25. 25Packets  Won’t go into details