1. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 111 Today’s class Instruction set architecture

2. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 112 Instruction Set Design The instruction set architecture (ISA) level is between the high-level languages and the hardware When new hardware architecture comes along …  Need to maintain backward compatibility  Can add new features to exploit new hardware capabilities

3. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 113 ISA Level

4. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 114 Properties of the ISA Level In principle, the ISA level is defined by how the machine appears to a machine language programmer In modern times, this is refined to say that ISA- level code is what a compiler outputs Compiler writer needs to know:  Memory model  What registers are available  What data types are available  What instructions are available

5. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 115 Memory Models Consider 8-byte (64-bit) words Do words have to be “word-aligned” (start at a word address)?

6. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 116 Instruction and Data Spaces Most machines have a single linear address space at the ISA level However, a few machines have separate address spaces for instructions and data  Effectively doubles memory!  All writes go to data space, protecting instructions from being overwritten

7. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 117 Registers Special purpose  Program counter  Stack pointer  Program status word General purpose  Hold key local variables and intermediate results of calculations  RISC machines usually have at least 32  Trend in new CPU designs is to have even more

8. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 118 Instructions LOAD and STORE instructions – move data between memory and registers MOVE instructions – move data among the registers Arithmetic instructions Boolean instructions Comparing data items and branching on the results

9. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 119 Pentium 4 Three operating modes  Real mode – all features added since the 8088 are turned off (effectively behaves like a simple 8088; if a program does something wrong whole machine crashes)  Virtual 8086 mode – makes it possible to run old 8088 programs in a protected way (if a program crashes, the OS is notified instead of the machine crashing)  Protected mode – actually behaves like a Pentium 4!

10. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1110 Pentium 4 Address space  16,384 segments  Each segment has 2 32 addresses (4 GB)  Most operating systems, including Unix and Windows, support only one segment  Every byte has its own address  Words are 32 bits long, and low-endian

11. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1111 Pentium 4 Registers  EAX is main arithmetic register  EBX holds pointers  ECX plays a role in looping  EDX used in multiplication and division  ESI – source string pointer  EDI – destination string pointer  EBP – base of the current stack frame  ESP – stack pointer  EIP – instruction pointer

12. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1112 Pentium 4 Data types  Two’s complement integers  Unsigned integers  Binary coded decimal numbers  IEEE 754 floating point numbers

13. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1113 Instruction Formats

14. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1114 Design Criteria Short instructions are better than long ones Sufficient room in the instruction format to express all the operations desired Number of bits in the address field

15. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1115 Examples Consider an (n + k) bit instruction that has a k- bit opcode and a single n-bit address  Allows for 2 k different operations  Allows for 2 n addressable memory cells Could alternatively have:  k-1 bit opcode and n+1 bit address  Half as many instructions but twice the addressable memory  k+1 bit opcode and n-1 bit address  Twice as many instructions but half the addressable memory

16. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1116 Expanding Opcodes An instruction with a 4-bit opcode and three 4-bit address fields.

17. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1117 Expanding Opcodes Suppose the designers need:  15 three-address instructions  14 two-address instructions  31 one-address instructions  15 no-address instructions Use opcodes 0-14 as the three-address instructions Interpret opcode 15 differently

18. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1118 Expanding Opcodes

19. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1119 Pentium 4 Instruction Formats Highly complex and irregular! Up to 6 variable-length fields, 5 of which are optional

20. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1120 Addressing Modes How to specify where an operand for an instruction is located How the bits of an address field in an instruction are interpreted

21. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1121 Immediate Addressing Address part of the instruction contains the actual operand itself An immediate instruction for loading 4 into register 1 Does not require an extra memory reference to fetch the operand

22. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1122 Direct Addressing Instruction specifies full address of the operand Instruction will always access the same memory location Useful for accessing global variables

23. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1123 Register Addressing Specifies a register for the operand Most common addressing mode on computers

24. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1124 Register Indirect Addressing Register contains the address in memory of the operand (the register acts as a pointer) The following example computes the sum of the elements of an array

25. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1125 Indexed Addressing Contents of a register plus a constant offset form the address of the operand Consider the following program for computing the OR of corresponding products in two arrays

26. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1126 Reverse Polish Notation Infix form: a + b Postfix form: a b + Any expression can be expressed without parentheses:  (a + b) * c = a b + c * Convenient for evaluating formulas using stacks on a computer

27. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1127 Reverse Polish Notation Some examples of infix expressions and their reverse Polish notation equivalents.

28. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1128 Evaluation of RPN Formulas Evaluation of (8 + 2 x 5) / (1 + 3 x 2 - 4) RPN form is 8 2 5 x + 1 3 2 x + 4 - /

29. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1129 Pentium 4 Addressing Modes Highly irregular Depends on which operating mode you are in (16-bit or 32-bit) Not all modes apply to all instructions Not all registers can be used in all modes Compiler writer’s nightmare!

30. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1130 Pentium 4 Addressing Modes

31. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1131 Data Movement Instructions Copying data is the most fundamental of all operations Four possibilities:  Register to register  Register to memory  Memory to register  Memory to memory May have one general instruction to cover all cases, or separate instructions for each case Need to indicate how much data to copy

32. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1132 Dyadic Operations Combine two operands to produce a result Arithmetic instructions Boolean instructions

33. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1133 Monadic Operations Have one operand and produce one result Shift and rotate instructions CLR, INC, NEG

34. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1134 Comparisons and Conditional Branches Common operation is a comparison to 0 Use bits in the PSW, such as C, N, Z

35. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1135 Other Instructions Procedure calls Loop control

36. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1136 Programmed Input/Output Single input instruction and single output instruction Selects an I/O device and a single character is transferred CPU must execute an explicit sequence of instructions for each and every character read or written

37. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1137 Programmed Input/Output A simple terminal might have four 1-byte registers Registers might be part of computer’s memory address space

38. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1138 Direct Memory Access DMA gets rid of most of the interrupts of programmed I/O

39. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1139 Pentium 4 Instructions

40. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1140 Pentium 4 Instructions

41. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1141 Pentium 4 Instructions

42. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1142 Pentium 4 Instructions

43. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1143 Pentium 4 Instructions

44. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1144 Flow of Control Most statements execute sequentially Branches alter statement flow Procedures also alter statement flow, but unlike branches, control is returned to the statement after the procedure call once the procedure is finished Recursive procedures are procedures that call themselves

45. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1145 The Towers of Hanoi An ancient problem with a simple recursive solution In a certain monastery in Hanoi there are 3 gold pegs Around the first peg are 64 gold disks, each disk slightly smaller in diameter than the disk below it The monks have to move the disks to the third peg, one disk at a time, but at no time may a larger disk sit on top of a smaller one It is said that when they finish the world will come to an end

46. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1146 5-Disk Initial Configuration

47. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1147 Solution Outline First move n-1 disks from peg 1 to peg 2 Now move 1 disk from peg 1 to peg 3 Then move the n-1 disks from peg 2 to peg 3

48. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1148 Solution This procedure moves n disks from peg I to peg j.

49. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1149 The Stack Need a stack to store the parameters and local variables for each invocation of a recursive procedure Do not want to confuse values of these variables in different invocations

50. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1150 The Stack

51. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1151 Procedure Calls

52. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1152 Coroutines

53. Informationsteknologi Friday, November 16, 2007Computer Architecture I - Class 1153 Interrupts