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CSE241 Formal Verification.1Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 5: File Formats.

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Presentation on theme: "CSE241 Formal Verification.1Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 5: File Formats."— Presentation transcript:

1 CSE241 Formal Verification.1Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 5: File Formats

2 CSE241 Formal Verification.2Cichy, UCSD ©2003 LEF - Explained  Library - Physical l Library Exchange Format (LEF) -Physical characteristics of the technology library –Abstracts of the standard cell library (ie. TSMC.18u) –Abstracts of all blocks and IO cells –Includes layer, via, placement site type -Timing characteristics of the technology library –Contains timing models for each pin of each component of the library

3 CSE241 Formal Verification.3Cichy, UCSD ©2003 Example LEF NAMESCASESENSITIVE OFF ; #TECHNOLOGY SECTION LAYER MET1 TYPE ROUTING ; PITCH 3.5 ; WIDTH 1.2 ; SPACING 1.4 ; DIRECTION HORIZONTAL ; RESISTANCE RPERSQ.7E-01 ; CAPACITANCE CPERSQDIST.46E-04 ; END MET1 LAYER VIA TYPE CUT ; END VIA LAYER MET2 TYPE ROUTING ; PITCH 4 ; WIDTH 1.8 ; SPACING 1.4 ; DIRECTION VERTICAL ; RESISTANCE RPERSQ.35E-01 ; CAPACITANCE CPERSQDIST.31E-04 ; END MET2

4 CSE241 Formal Verification.4Cichy, UCSD ©2003 DEF Explained  Design - Physical l Design Exchange Format (DEF) -Physical characteristics of the cells –Macros of design –Placement information –Pin locations –Metal blockages –Orientation

5 CSE241 Formal Verification.5Cichy, UCSD ©2003 DEF  DEF l Contains the design-specific information of a circuit and is a representation of the design at any point during the layout process l DEF file is an ASCII representation S l Syntax conventions conveys logical design data to, and physical design data from, place-and-route tools l Can include internal connectivity grouping information, and physical constraints l Physical: -Placement locations and orientations -Routing geometry data -Logical design changes for backannotation. l Place-and-route tools can read physical design data -For performing ECO changes –Clock gen –Optimization –SI based l Floorplan -ROWS, TRACKS, GCELLGRID, and DIEAREA

6 CSE241 Formal Verification.6Cichy, UCSD ©2003 DEF Structure VERSION statement NAMESCASESENSITIVE statement DIVIDERCHAR statement BUSBITCHARS statement DESIGN statement [ TECHNOLOGY statement ] [ UNITS statement ] [ HISTORY statement ]... [ PROPERTYDEFINITIONS section ] [ DIEAREA statement ] [ ROWS statement ]... [ TRACKS statement ]... ………..  Standard DEF files can contain the following statements and sections. You must specify the statements and sections in the following order. ….. [ GCELLGRID statement ]... [ VIAS statement ] [ REGIONS statement ] COMPONENTS section [ PINS section ] [ PINPROPERTIES section ] [ BLOCKAGES section ] [ SLOTS section ] [ FILLS section ] [ SPECIALNETS section ] NETS section [ SCANCHAINS section ] [ GROUPS section ] [ BEGINEXT section ] END DESIGN statement

7 CSE241 Formal Verification.7Cichy, UCSD ©2003 Example DEF PROPERTYDEFINITIONS DESIGN HSNAPGRID STRING "-1653120 1120 2954" ; DESIGN VSNAPGRID STRING "-1653960 1320 2508" ; DESIGN VERILOGDESIGNNAME STRING "cds_vbin.aes_cipher_cores_top_2:hdl" ; DESIGN GCFLIBRARY_TIMESTAMP STRING "1045714484" ; DESIGN GCFLIBRARY STRING "../gcf_out" ; END PROPERTYDEFINITIONS DIEAREA ( -1653960 -1653120 ) ( 1655280 1654240 ) ; ROW ROW_168 tsm3site -852720 842240 N DO 1293 BY 1 STEP 1320 0 ; ROW ROW_167 tsm3site -852720 832160 FS DO 1293 BY 1 STEP 1320 0 ; ROW ROW_166 tsm3site -852720 822080 N DO 1293 BY 1 STEP 1320 0 ; ROW ROW_165 tsm3site -852720 812000 FS DO 1293 BY 1 STEP 1320 0 ;

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