1. 7-Segment Displays Digilent Spartan 3 Board Discussion DS-4.2

2. Spartan 3 Board

4. Turning on an LED Note: A zero turns on the LED

5. Spartan 3 Board

6. 7-Segment Decoder a-g LOW to turn on segment

7. Multiplex displays

8. 0 1 1 1 0 0 0 0 1 1 0

9. Multiplex displays 1 0 1 1 0 0 0 1 1 1 1

10. Multiplex displays 1 1 0 1 1 0 0 1 1 0 0

11. Multiplex displays 1 1 1 0 0 1 1 1 0 0 0

12. x7seg

13. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity x7seg is Port ( x : in std_logic_vector(15 downto 0); cclk, clr : in std_logic; Aen : in std_logic_vector(3 downto 0); AtoG : out std_logic_vector(6 downto 0); AN : out std_logic_vector(3 downto 0) ); end x7seg; x7seg.vhd

14. architecture arch_x7seg of x7seg is signal dig0, dig1, dig2, dig3: std_logic_vector(3 downto 0); signal digit : std_logic_vector(3 downto 0); signal count : std_logic_vector(1 downto 0); constant bus_width: positive := 4; begin

15. use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ctr2bit is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (1 downto 0) ); end ctr2bit; architecture ctr2bit_arch of ctr2bit is signal COUNT: STD_LOGIC_VECTOR (1 downto 0); begin process (clk, clr) begin if clr = '1' then COUNT <= "00"; elsif clk'event and clk='1' then COUNT <= COUNT + 1; end if; end process; q <= COUNT; end ctr2bit_arch;

16. library IEEE; use IEEE.std_logic_1164.all; entity ANcode is port ( Aen: in STD_LOGIC_VECTOR (3 downto 0); Asel: in STD_LOGIC_VECTOR (1 downto 0); AN: out STD_LOGIC_VECTOR (3 downto 0) ); end ANcode;

17. architecture ANcode_arch of ANcode is begin process(Aen, Asel) begin AN <= "1111"; case Asel is when "00" => if Aen(0) = '1' then AN <= "1110"; end if; when "01" => if Aen(1) = '1' then AN <= "1101"; end if; when "10" => if Aen(2) = '1' then AN <= "1011"; end if; when others => if Aen(3) = '1' then AN <= "0111"; end if; end case; end process; end ANcode_arch;

18. u0: ctr2bit port map (clr => clr, clk => cclk, q => count); u1: mux4g generic map(width => bus_width) port map (a => dig0, b => dig1, c => dig2, d => dig3, sel => count, y => digit); u2: seg7dec port map (q => digit, AtoG => AtoG); u3: ANcode port map (Aen => Aen, Asel => count, AN => AN); Port Maps

19. NET "AN " LOC = "E13" ; NET "AN " LOC = "F14" ; NET "AN " LOC = "G14" ; NET "AN " LOC = "d14" ; NET "AtoG " LOC = "E14" ; NET "AtoG " LOC = "G13" ; NET "AtoG " LOC = "N15" ; NET "AtoG " LOC = "P15" ; NET "AtoG " LOC = "R16" ; NET "AtoG " LOC = "F13" ; NET "AtoG " LOC = "N16" ; NET "dp" LOC = "P16" ;.ucf file