1. Built-in Adaptive Test and Calibration of DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL 36849 18 th IEEE North Atlantic Test Workshop 2009

2. Outline Overview Previous Work Proposed BIST Scheme Adaptive Self-Calibration of DAC Simulation Results Conclusion NATW'092

3. Overview Proposed design-for-testability (DFT) architecture for a mixed-signal SoC –Accuracy –Performance –Cost Test of on-chip DAC and ADC –Linearity (DNL/INL) –Resolution and speed –Signal-to-noise ratio (SNR) NATW'093

4. A Typical Mixed-Signal BIST for SoC* NATW'094 * F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

5. Previous Work NATW'095 W. Jiang and V.D. Agrawal, Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC, NATW’08

6. Non-linearity Errors NATW'096 Non-linearity error Non-linearity error

7. Proposed BIST Scheme NATW'097

8. Proposed BIST Scheme (Cont.) DSP for BIST control Components –1-bit first-order sigma-delta modulator –Low-pass filter (integrator or comb filter) –Adaptive polynomial evaluation/fix circuit –Low-resolution dithering DAC –Loop-back circuitry connecting internal DAC and ADC NATW'098

9. Testing and characterization of DAC NATW'099

10. Testing of DAC (Cont.) Response and ramp input compared for INL error INL error analyzed by adaptive polynomial fitting algorithm Best matching polynomials selected for various and DAC profiles Test results indicated by calculated characteristics (offset, gain and harmonic distortion, etc) Polynomial coefficients calculated for dithering DAC to improve INL NATW'0910

11. Polynomial Fitting Introduced by Sunter et al. in ITC’97 and A. Roy et al. in ITC’02 Summary: –Divide DAC transfer function into four sections –Combine function outputs of each section (S0, S1, S2, S3) –Calculate four coefficients (b0, b1, b2, b3) by easily- generated equations NATW'0911

12. Third-Order Polynomial NATW'0912

13. First- and second-order Polynomial NATW'0913 First-order polynomial Second-order polynomial

14. Adaptive Polynomial Fitting Fitting INL error from lower order polynomial to higher order Calculate RMS error of each polynomial Select the polynomial with least RMS error (when RMS error rising with higher order polynomial) NATW'0914

15. Sigma-Delta Modulator NATW'0915 1-bit first-order sigma-delta modulator Transfer function in z-domain

16. Sigma-Delta Modulator (Cont.) NATW'0916 First-order Second-order Third-order 17-bit ENOB 104.1dB Oversampling ratio (OSR) SNR (dB)

17. Dithering DAC NATW'0917 3 α=1 17bits Resolution of dithering-DAC (bits) Estimated DAC resolution (bits) Oversampling ratio (OSR) 2

18. Simulation of DAC Test NATW'0918 14-bit DAC 16K ramp codes INL error up to ±1.5dB Indices of 14-bit DAC-under-test INL of 14-bit DAC (LSB)

19. Simulation (Cont.) NATW'0919 Fitting results by different order polynomial Indices of 14-bit DAC-under-test INL of 14-bit DAC (LSB)

20. Best-matching Polynomial NATW'0920

21. Conclusion A built-in self-test and self-calibration solution for mixed-signal SoC is proposed A polynomial fitting algorithm is employed for INL error correction Fault-tolerance levels can be chosen for various applications Simulation results show significant improvement in linearity after calibration NATW'0921

22. Q&A Thank you! NATW'0922