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מבנה המחשב – מבוא למחשבים ספרתיים Foundations of Combinational Circuits תרגול מספר 3
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Checking a Circuit Mapping the circuit into a directed graph G(V,E). Each gate is a vertex Each output terminal defines a net Each net is transformed into edges from the output terminal to each of the input terminals. OR AND NOT XOROUT IN Single net
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Graph Representation by List of Neighbors 6 7 8 3 4 5 2 13586 756 28
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Graph Representation by Matrix v v v 12345 1 2 3 4 5
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Checking a Circuit If a terminal has two incoming edges, then it is fed by two nets, which is illegal. In that case we stop and return FALSE. OR AND NOT XOROUT IN Two inputs to one terminal !
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Testing for Circles In order to test for circles we need to run a Depth-First-Search (DFS) algorithm on the graph, and check for any backwards edges during the execution of the algorithm.
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DFS Example 1 2 4 5 3 Stack
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DFS 1 1 2 4 5 3 Stack = Currently in the stack
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DFS 1 2 1 2 4 5 3 Stack
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DFS 1 2 3 1 2 4 5 3 Stack
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DFS 1 2 3 1 2 4 5 3 4 Stack Backwards Edge This graph has a cycle!
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Elements of the Proof The algorithm terminates regardless of the structure of the input graph. If there is a cycle in the graph, the algorithm will find it (return FALSE). If there is no cycle in the graph, the algorithm will return TRUE.
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The Algorithm Terminates The algorithm passes through every vertex only once, therefore it will always terminate after visiting all of the vertices regardless of the edges.
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The Proof Assume there is a cycle in the graph. At some point a first vertex that belongs to the cycle will be reached. All other vertices of the cycle have not been reached yet. Before that first vertex is popped out of the stack, the DFS procedure guarantees that an edge closing the cycle and entering that vertex will be tested. It is a backwards edge.
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The Proof Immediate, but nevertheless: Assume there are no cycles in the graph. Backwards edges cannot exist since they require a path from a successor to a predecessor, which means there is a cycle.
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Topological Sort Works only on Directed Acyclic Graphs (DAG). The Algorithm: –Form a set of all independent vertices - those that have no incoming edges. There must be at least one! –While the set is empty: Pick any vertex v from the set. If any of its successors have no other predecessors – add them to the set of independent vertices. Erase all of the edges originating at v.
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Topological Sort Example OR AND NOT XOROUT IN = Independent Vertex
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN OR
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN ORAND
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN ORANDNOT
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN ORANDNOTXOR
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Topological Sort Example OR AND NOT XOROUT IN The Topological Sort: IN ORANDNOTXOROUT
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Testing for Cycles during Topological Sort OR AND NOT XOROUT IN There are nodes left, but none are independent Cycle!
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Propagation Delay There is always at least one “critical path”. What is the propagation delay of a circuit that is not acyclic?
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Finding the Propagation Delay Now, using the fact that it is an acyclic graph, we go through the topological order from start to beginning, each time updating the “inputs ready” time of the successors. The total propagation delay is the maximal “inputs ready” time (assuming that we used output nodes).
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Finding the Maximum Delay 00ORANDNOTXOROUT
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A circuit with 2 n/2 paths 2 options n/2 stages with 2 options each, resulting in 2 n/2 paths. How are we computing the delay of an exponential number of circuits in linear time? Let’s go to the previous slide.
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A circuit with 2 n paths …cannot be built! Why? A combinational circuit is a DAG, therefore we cannot reorder the gates to create different paths. Our only option is to include or exclude gates to create different paths. But, having n gates, we only have 2 n such paths. Each gate can be included or excluded, therefore 2 n. We cannot build this circuit since we will require an unbounded in-degree of the gates.
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XOR is Associative – part I Definition 1 st Expanded definition De Morgan Distributive Complement Distributive
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XOR is Associative – part 2 Definition 2 nd Expanded definition De Morgan Distributive Complement Distributive
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THE END
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