1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 313 - Computer Organization Multi-Cycle Processor Design 2 Fall 2005 Reading: 5.6 - 5.11, C.4 - C.5 HW Due Fri. 5/11: 5.32, 5.34, 5.35, 5.47, 5.49, 5.55 Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s 18-347 Slides - Fall 1999 CMU other sources as noted

2. Fall 2005Multicycle Design 22 Outline - Multicycle Design  Overview  Datapath Design  Controller Design  Aside: FSM Design in Verilog   Performance Considerations  Extending the Design: An Example  Microprogramming  Exceptions

3. Fall 2005Multicycle Design 23 Review State Machine Design  Traditional Approach:  Create State Diagram  Create State Transition Table  Assign State Codes  Write Excitation Equations & Minimize  HDL-Based State Machine Design  Create State Diagram (optional)  Write HDL description of state machine  Synthesize

4. Fall 2005Multicycle Design 24 Review - State Transition Table / Diagram  Transition List - lists edges in STD PSConditionNSOutput IDLEARM' + DOOR'IDLE0 IDLEARM*DOORBEEP0 BEEPARMWAIT1 BEEPARM'IDLE1 WAITARMBEEP0 WAITARM'IDLE0 IDLE BEEP Honk=1 WAIT ARMDOOR ARM ARM’ ARM’ + ARMDOOR’ = ARM’ + DOOR’ ARM’

5. Fall 2005Multicycle Design 25 Example: MIPS Control Unit

6. Fall 2005Multicycle Design 26 Review: Full Multicycle Implementation

7. Fall 2005Multicycle Design 27 Controller Implementation  Typical Implementation: Figure 5-37, p. 338  Variations  Random logic  PLA  ROM address lines = inputs data lines = outputs contents = “truth table” Datapath control outputs Inputs from Instr. Reg (opcode) Combinational Control Logic State Next State

8. Fall 2005Multicycle Design 28 Outline - Multicycle Design  Overview  Datapath Design  Controller Design  Aside: FSM Design in Verilog  Performance Considerations   Extending the Design: An Example  Microprogramming  Exceptions

9. Fall 2005Multicycle Design 29 Performance of a Multicycle Implementation  What is the CPI of the Multicycle Implementation?  Using measured instruction mix from SPECINT2000 lw5 cycles25% sw4 cycles10% R-type4 cycles52% branch3 cycles11% jump3 cycles2%  What is the CPI?  CPI = (5 cycles * 0.25) + (4 cycles * 0.10) + (4 cycles * 0.53) + (3 cycles * 0.11) + (3 cycles * 0.02)  CPI = 4.12 cycles per instruction

10. Fall 2005Multicycle Design 210 Performance Continued  Assuming a 200ps clock, what is average execution time/instruction?  Sec/Instr = 4.12 CPI * 200ps/cycle) = 824ps/instr  How does this compare to the Single-Cycle Case?  Sec/Instr = 1 CPI * 600ps/cycle = 600ps/instr  Single-Cycle is 1.38 times faster than Multicycle  Why is Single-Cycle faster than Multicycle?  Branch & jump are the same speed (600ps vs 600ps)  R-type & store are faster (600ps vs 800ps)  Load word is faster (600ps vs 1000ps)

11. Fall 2005Multicycle Design 211 Outline - Multicycle Design  Overview  Datapath Design  Controller Design  Aside: FSM Design in Verilog  Performance Considerations  Extending the Design: An Example   Microprogramming  Exceptions

12. Fall 2005Multicycle Design 212 Multicycle Example Problem  Extend the design to implement the “jr” (jump register) instruction: jr rsPC = Reg[rs]  Format:  Steps: 1.Review instruction requirements (register transfer) 2.Modify datapath 3.Modify control logic 0rs0080 6 bits5 bits 6 bits

13. Fall 2005Multicycle Design 213 Reg[rs] Example Problem: Datapath What needs to be changed? 3 2 1 0

14. Fall 2005Multicycle Design 214 Example Problem: Control What needs to be changed? PCWrite PCSource = 11 (OP = ‘JR‘) 0 Instruction Fetch Instruction decode / register fetch 1 2 Memory address computation 3 4 57 689 Execution Branch Completion Jump Completion Memory access Memory access R-type completion Writeback step Start MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 (OP = ‘LW’) (OP = (‘SW’) MemRead IorD = 1 RegWrite MemToReg=1 RegDst = 0 MemWrite IorD = 1 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RegDst = 1 RegWrite MemtoReg = 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 PCWrite PCSource = 10 Op=LW or SW Op=R-type Op=BEQ Op=J

15. Fall 2005Multicycle Design 215 Outline - Multicycle Design  Overview  Datapath Design  Controller Design  Aside: FSM Design in Verilog  Performance Considerations  Extending the Design: An Example  Microprogramming   Exceptions

16. Fall 2005Multicycle Design 216 Control Implementation - Another View  Separate Logic into two pieces  Output Logic (this is a Moore Machine - why?)  Next-State Logic

17. Fall 2005Multicycle Design 217 Microprogramming - Motivation  Problems with graphical approach to FSM Design  Unwieldy for large number of states (real processors may have hundreds of instructions -> hundreds of states)  Unwieldy if instruction types vary radically (can you say… x86?)  Most states are sequential (state 4 follows state 3; state 3 follows state 2; state 7 follows state 6; etc.  Idea: expand on ROM implementation of control

18. Fall 2005Multicycle Design 218 Consider Output Logic in ROM  ROM Characteristics - "lookup table"  State code for each state is a ROM address  Control outputs for each state are a ROM word

19. Fall 2005Multicycle Design 219 Microprogramming - Basic Idea  Idea: expand on ROM control implementation  One state = one ROM word = one microinstruction  State sequences form a microprogram  Each state code becomes a microinstruction address

20. Fall 2005Multicycle Design 220 Microprogramming - Sequencer Design Datapath Control Outputs Microcode Storage (ROM) n µPC Microinstruction address Dispatch ROM 2 Inputs from IR (Opcode) n Sequence Control Microinstruction + 1 n n Dispatch ROM 1 0 n 0 1 2 3

21. Fall 2005Multicycle Design 221 Describing Microcode  Each microinstruction is lots of 1's and 0's  To ease understanding:  Break into fields related to different datapath functions  Use mnemonics to describe different field values Datapath Control Signals ALU controlSequencingLabel AddRead PCALUSeqstring Subt Func Code PC A B 4 Extend Extshft Read Write ALU Write MDR Read ALU Write ALU ALUOut-cond Jump address Fetch Dispatch i See also: Figure C.5.1, p. C-28 SRC1Reg. controlMemoryPCWrite control ALUOp ALUSrcA ALUSrcB RegWrite RegDst MemRead SRC2 MemWrite IRWrite PCWrite PCWriteCond IorD PCSource MemtoReg AddrCtl Sequencer Control Signal

22. Fall 2005Multicycle Design 222 Microcode for Multicycle Implementation

23. Fall 2005Multicycle Design 223 Sequencer Implementation Details

24. Fall 2005Multicycle Design 224 Microcoding Tradeoffs +Makes design easier +Flexible  Easy to adapt to changes in organization, timing, technology  Can make changes late in design cycle  Can add more instructions just by adding microcode -Costly to implement -Slow - "extra level" of interpretation

25. Fall 2005Multicycle Design 225 Microcoding Perspective  Not used in modern RISC processors  simple instructions -> simple control  hardwired control -> faster execution  pipelining used to enhance performance  Used heavily in CISC processors  Traditional CISC: all instructions microcoded multiple dispatch ROMs to handle different instruction classes, addressing modes, etc.  Current CISC (see Section 5.9) Microinstructions pipelined like RISC instructions! Simple instructions translate to one microinstruction Complex instructions translate to multiple microinstructions

26. Fall 2005Multicycle Design 226 Instruction Decoding in the Pentium 4 Source: “The Microarchitecture of the Pentium® 4 Processor”, Intel Technology Journal, First Quarter 2001 http://developer.intel.com/technology/itj/q12001/articles/art_2.htm.

27. Fall 2005Multicycle Design 227 Instruction Decoding in the Pentium 4 Source: “The Microarchitecture of the Pentium® 4 Processor”, Intel Technology Journal, First Quarter 2001 http://developer.intel.com/technology/itj/q12001/articles/art_2.htm.

28. Fall 2005Multicycle Design 228 Coming Up  Implementing Exceptions  Pipelined Design