1. 1 The Designs and Analysis of a Scalable Optical Packet Switching Architecture Speaker: Chia-Wei Tuan Adviser: Prof. Ho-Ting Wu 3/4/2009

2. 2 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

3. 3 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

4. 4 Contention resolution in switches Contention resolution is an important issue when several packets contend for a common network resource. Contention resolution is an important issue when several packets contend for a common network resource. When two input packets are destined for the same output port simultaneously, packet contention occurs. When two input packets are destined for the same output port simultaneously, packet contention occurs. When contention occurs, storing packets into the switch buffers becomes the most general technique. When contention occurs, storing packets into the switch buffers becomes the most general technique.

5. 5 Contention resolution in switches At present, optical storage technology is not available. At present, optical storage technology is not available. Thus, switching operations are done electronically, forcing the optical signal to be converted to an electronic format. Thus, switching operations are done electronically, forcing the optical signal to be converted to an electronic format. But, in all-optical networks, packets are switched optically until they reach their destination. But, in all-optical networks, packets are switched optically until they reach their destination. That is, switching must also be optical in all-optical networks. That is, switching must also be optical in all-optical networks.

6. 6 How to store packets in all-optical networks? Switched delay lines (SDL). Switched delay lines (SDL). Storing of packets in fiber DLs act as transient optical buffers. Storing of packets in fiber DLs act as transient optical buffers. Quadro is a single-buffer DL switching architecture. Quadro is a single-buffer DL switching architecture. M-Quadro is a multi-buffer Quadro architecture that uses a longer DL to increase the buffering capacity. M-Quadro is a multi-buffer Quadro architecture that uses a longer DL to increase the buffering capacity.

7. 7 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

8. 8 B-Quadro Switching Architecture The length of DL i is m i. The length of DL i is m i. The (m 2 -m 1 )th slot in DL 2 counting from left to right is termed “virtual slot”, if m2 > m1. The (m 2 -m 1 )th slot in DL 2 counting from left to right is termed “virtual slot”, if m2 > m1.

9. 9 Left control strategy (LCS) Ex1: Ex1: LCS applied: LCS applied:

10. 10 Right control strategy (RCS) Ex2: Ex2: RCS applied: RCS applied:

11. 11 Virtual-slot control strategy (VCS) VCS is to ensure, whenever possible, that outgoing state 1 be different from outgoing state 2. VCS is to ensure, whenever possible, that outgoing state 1 be different from outgoing state 2. Deflection: Deflection: Internal blocking: Internal blocking:

12. 12 Virtual-slot control strategy (VCS) Ex1: Ex1: VCS applied: VCS applied:

13. 13 Virtual-slot control strategy (VCS) Ex2: Ex2: VCS applied: VCS applied:

14. 14 The limitations of M-Quadro Ex3: Ex3: VCS applied: VCS applied:

15. 15 The M-B-Quadro Architecture The packets through the bypass line (BL) are carried without delay. (No buffering capability) The packets through the bypass line (BL) are carried without delay. (No buffering capability)

16. 16 Example of M-B-Quadro Ex3: Ex3: LAVS applied: LAVS applied:

17. 17 Multi-stage Multi-buffer Bypass Quadro (M 2 -B-Quadro) Switch Architecture 3 x 3 switch: 3 x 3 switch: n x n n x n switch: switch:

18. 18 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

19. 19 The Comparsion between M-Qdadro and M-B-Qdadro with Symmetrical Traffic

20. 20 The Parameter of Asymmetrical Traffic The load of each input is ρ. The load of each input is ρ. Let X be a random variable that indicates the state of a input port. Let X be a random variable that indicates the state of a input port. P(X=i) represents the probability of the packet destined for output port i at specific time slot. P(X=i) represents the probability of the packet destined for output port i at specific time slot. P(X=0) = 1- ρ. P(X=0) = 1- ρ. P(X=1) = R 1 * ρ. P(X=1) = R 1 * ρ. P(X=2) = R 2 * ρ. P(X=2) = R 2 * ρ. where R i is the ratio of total packets to the packets destined for output port i.where R i is the ratio of total packets to the packets destined for output port i.

21. 21 The Comparsion between M-Qdadro and M-B-Qdadro with Nonbursty and Asymmetrical Traffic

22. 22 The Comparsion between M-Qdadro and M-B-Qdadro with Bursty and Asymmetrical Traffic

23. 23 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

24. 24 Bursty Traffic Model Pa: The probability of no packet arriving in the next slot, given the current slot is idle. Pa: The probability of no packet arriving in the next slot, given the current slot is idle. Pb: The probability of the next arrival will be part of the burst. (i.e., destined to the same destination). Pb: The probability of the next arrival will be part of the burst. (i.e., destined to the same destination).

25. 25 The properties of Bursty Traffic Model Expected bursty length = Expected bursty length = Offered load at each input port = Offered load at each input port =

26. 26 Asymmetric Traffic Model In realistic networks, the traffic is not only bursty but also asymmetric. In realistic networks, the traffic is not only bursty but also asymmetric. Back to P32

27. 27 How to determine the value of P 01 and P 02 ? Calculus the steady state distribution: Calculus the steady state distribution: P(X=i) can be derived by summing the steady-state probability in {bursty1, destination i} and {bursty2, destination i} states. P(X=i) can be derived by summing the steady-state probability in {bursty1, destination i} and {bursty2, destination i} states. After rearranging, After rearranging, we obtain: we obtain: Back to P32

28. 28 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

29. 29 Exact Analytical Model is the state (i.e., destination) of slot j at DL i. is the state (i.e., destination) of slot j at DL i. The state of input port i is represented as x i. The state of input port i is represented as x i. The state definition of exact DTMC. The state definition of exact DTMC.

30. 30 Control Strategies Let and are two instances of. Let and are two instances of. Define control strategy as, where is part of control strategy which determine the next incoming slot i. Define control strategy as, where is part of control strategy which determine the next incoming slot i. Assuming is the next state of, the relation of them is: Assuming is the next state of, the relation of them is:

31. 31 The General Formula of State Transition Matrix

32. 32 State Transition Matrix In Non-bursty Traffic Case In non-bursty traffic case, In non-bursty traffic case, Thus, state transition probability in can be reduced to Thus, state transition probability in can be reduced to The non-bursty case can be further divided into The non-bursty case can be further divided into 1)Symmetrical case: Set to 1/n for k=1,2,…, n. 2)Asymmetrical case: Set to some probability greater or smaller than 1/n for k=1,2,…, n

33. 33 State Transition Matrix In Bursty Traffic Case In bursty traffic case, it can also be further divided into In bursty traffic case, it can also be further divided into 1)Symmetrical case: Set P(x=1) = P(x=2). 2)Asymmetrical case: Set P(x=1) ≠ P(x=2). where is the transition probability in the traffic model diagram. where is the transition probability in the traffic model diagram.diagram in the equation in the equation

34. 34 Calculus Steady State Let be steady state distribution. Let be steady state distribution. where is the space size. Compute iteratively Compute iteratively until Deflection probability: Deflection probability:

35. 35 Approximate Asymptotic Model Goal: get the lowest bound of deflection probability. Goal: get the lowest bound of deflection probability. Unlimited delay line size. Unlimited delay line size. The approximate asymptotic model assume that The approximate asymptotic model assume that m1 = m2 = … = m n-1 = 1 and m n = ∞.

36. 36 Estimation Redefine the state definition of DTMC as Redefine the state definition of DTMC as Estimation: Estimation: Back

37. 37 An Iterative Method to calculus the steady state distribution 1) Initial: 2) Calculus state transition probability matrix:

38. 38 An Iterative Method to calculus the steady state distribution 3) Calculus the next state distribution vectors. 4) Check the convergence condition.  If the condition holds, stop the program and compute deflection probability.  Otherwise, calculus the new estimate conditional probability and go to step 2) estimate

39. 39 Outline Introduction Introduction Switching Architecture and Control Strategies Switching Architecture and Control Strategies Performance Results Performance Results Input Traffic Model Input Traffic Model Queueing Analysis Queueing Analysis Numerical Results for Queueing Analysis Model Numerical Results for Queueing Analysis Model

40. 40 Exact model and simulation for Symmetrical Traffic M 1 =1, M 2 =4. M 1 =1, M 2 =4. Using LAVS control strategy. Using LAVS control strategy.

41. 41 Exact model and simulation for Asymmetrical Traffic M 1 =1, M 2 =4. M 1 =1, M 2 =4. Using LAVS control strategy. Using LAVS control strategy. Expected bursty length = 20. Expected bursty length = 20.

42. 42 Lowest bound of deflection probability. Under a specific traffic condition, we obtain the lowest bound of deflection prob. Under a specific traffic condition, we obtain the lowest bound of deflection prob. bursty length = 5 and offered load = 0.6 : bursty length = 5 and offered load = 0.6 :

43. 43 Conclusions M-B-Quadro can achieve lower packet deflection probability. M-B-Quadro can achieve lower packet deflection probability. The analytical model can evaluate the system performances under non-bursty, bursty, symmetrical, and asymmetrical conditions. The analytical model can evaluate the system performances under non-bursty, bursty, symmetrical, and asymmetrical conditions. The numerical results show the analytical model is successful to reveal the lowest bound of deflection probability in this switching architecture. The numerical results show the analytical model is successful to reveal the lowest bound of deflection probability in this switching architecture.

44. 44 Reference [1]Chlamtac, I. and Fumagalli, and Suh, C. J., 2000, “Multibuffer Delay Line Architecture for Efficient Contention Resolution in Optical Switching Nodes,” IEEE Transactions on Communications, Vol. 48, No. 12, pp. 2089- 2098. [1]Chlamtac, I. and Fumagalli, and Suh, C. J., 2000, “Multibuffer Delay Line Architecture for Efficient Contention Resolution in Optical Switching Nodes,” IEEE Transactions on Communications, Vol. 48, No. 12, pp. 2089- 2098. [2]Haas, Z., 1993, “The Staggering Switch - An Electronically Controlled Optical Packet Switch,” IEEE/OSA Journal of Lightwave Technology, Vol. 11, No. 5/6, pp. 925-936. [2]Haas, Z., 1993, “The Staggering Switch - An Electronically Controlled Optical Packet Switch,” IEEE/OSA Journal of Lightwave Technology, Vol. 11, No. 5/6, pp. 925-936. [3]Wang-Rong Chang, Ho-Ting Wu, Kai-Wei Ke, and Hui-Tang Lin, “The Designs of a Scalable Optical Packet Switching Architecture”, Journal of the Chinese Institute of Engineers, vol. 31, no. 3, pp. 469-479, 2008. [3]Wang-Rong Chang, Ho-Ting Wu, Kai-Wei Ke, and Hui-Tang Lin, “The Designs of a Scalable Optical Packet Switching Architecture”, Journal of the Chinese Institute of Engineers, vol. 31, no. 3, pp. 469-479, 2008.

45. 45 Thank you! Q&A