1. 1 Reconfigurable Systems - Conceptual Design Review

2. 2 Reconfigurable Systems Team  Chris Canine  Terseer Ityavyar  Cameron D. Dennis Client / Faculty Mentor  Dr. Greg Donohoe Lead Instructor  Dr. Joe Law Graduate Mentor  John Geidl Sponsor  NASA  UI CAMBR

3. 3 Background

4. 4 Embedded Computing Invisible to the user  Example: The modern day vehicle has about 40 microprocessors Goal: High speed with smallest footprint  Small footprint Size Weight Power consumption  Speed (computing power) Linear system  Computing is done logically  Resources take up memory

5. 5 Reconfigurable Computing System Massive data path parallelism Do many tasks at once Flexibility is gained through reconfiguration  Processing Elements (PE’s)  Interconnect IOP1 PE4 PE0 PE3 PE2 PE1 FirePE0 FireIOP0 FireIOP1 IOP0 FirePE1 FirePE2 FirePE3 Input Output

6. 6 Reconfigurable Interconnect Current technology uses shared, parallel buses  Limited throughput with high power consumption Proposed technology uses dedicated, serial data paths with crossbar switching  Very high throughput  Low power consumption Crossbar Switching Picture from National Semiconductor’s “LVDS Owner’s Manual”

7. 7 Last Year’s S.D. Project Global Clock Processor Node Configurable Memory Module Interconnect Control

8. 8 ULP 0.5V New approach LVDS signaling Serial routing ULP 0.5V XBAR serializer deserializer LVDS Data source Data sink LVDS Old approach LVCMOS signals Parallel routing LVCMOS 2.5V XBAR Data source Data sink LVCMOS Strategy

9. 9 Low Voltage Differential Signaling How it works:  Switch current direction  Input current sense detection Routing:  Dedicated forward and return signal lines  Tailored transmission line characteristics, field cancellation  Minimize frequency effects, reflection and signal distortion ‘0’ ‘1’ ZLZL ZLZL Sender Receiver

10. 10 Low Voltage Differential Signaling Noise sensitivity:  Reduced crosstalk  Robust, excellent common- mode noise rejection  Low voltage (350 mV), higher frequencies (>1.5 GHz)  Smaller voltage swings Power consumption:  Lower, relatively independent of switching frequency  To minimize power per bit, maximize data rate through each serial channel 0 2.5 Standard CMOS +0.175 -0.175 LVDS

11. 11 What We Will Do

12. 12 Our Goal To compare serial communication versus parallel communication Show that Low Voltage Differential Signaling (LVDS) communication is a viable implementation method Highlight the benefits of LVDS including  High-speed data transfer  Lowered Electro-Magnetic Interference (EMI)  Low power consumption  Reduced circuit board area

13. 13 Needs A study that will  Convince a spacecraft system engineer to use serial LVDS designs for reconfigurable systems  Provide the documentation to allow the implementation of serial LVDS designs

14. 14 Constraints No slower than 800 data Mbits per second Variable path delay Function with different delays in the communication path No errors detected in a bit error rate test (BERT) in 15 minutes of continuous operation Preferred all on one printed circuit board

15. 15 Specifications Proof of concept  Compare differential, sequential communication vs. single-ended, parallel communication.  Power consumption – “Gigahertz @ milliWatts” Reduced watts per bit  Circuit board area – Show a greatly reduced area vs. parallel system

16. 16 Specifications (cont.) Two Source Nodes Two Destination Nodes  Transmit from either source to either destination depending on a specific control signal sent to switch the central crosspoint switch Desirable  Go to two destinations from one source  Full bidirectional communication

17. 17 Deliverables Reports  Compare serial vs. parallel implementations for power and area  Describe a design flow using the Cadence Tools  Proper documentation to pass on to someone else to duplicate the design

18. 18 Deliverables (cont.) Hardware  Demo a working serial system meeting the specifications above  Instrument as necessary to demonstrate the specifications Measure and report Bit Error Rate (BERT) Measure and report power consumption

19. 19 Design Implementation Options

20. 20 Components Needed 4 Field Programmable Gate Arrays (FPGA) 4 Serializer/Deserializer’s (SerDes) 1 Crosspoint Switch (XBAR) LCD Displays

21. 21 Option A Offboard FPGA Onboard SerDes Can use D2SB & DIO5  Already assembled  Easy setup  LCD included  Relative low cost  Will reduce Speed  Complicated pinout SER FPGA DES FPGA XBAR SER FPGA DES FPGA

22. 22 Option A Specifics Offboard FPGA  Digilent D2SB/DIO5 Kit with Xilinx Spartan IIE FPGA Onboard SerDes  National Semiconductor DS92LV18 Onboard Crosspoint Switch  National Semiconductor SCAN90CP02 Additional Onboard Hardware  LCD and other display hardware is included on the D2SB/DIO5 board

23. 23 Option B Onboard FPGA’s Onboard SerDes  SerDes will allow faster onboard communications  Less noise / interference  Smaller board area  Requires more components  Complicated layouts and chip placements SER FPGA DES FPGA XBAR SER FPGA DES FPGA

24. 24 Option B Specifics Onboard FPGA  Xilinx Spartan IIE FPGA Onboard SerDes  National Semiconductor DS92LV18 Onboard Crosspoint Switch  National Semiconductor SCAN90CP02 Additional Onboard Hardware  LCD to display BERT results

25. 25 Option C Onboard FPGA’s Use built-in SerDes capability of FPGA’s  Least amount of components  More difficult VHDL implementation  FPGA with these abilities is very expensive  Less interconnect = less noise introduction  Smallest board size FPGA XBAR FPGA

26. 26 Option C Specifics Onboard FPGA  Xilinx Virtex Family FPGA Onboard SerDes  None Required Onboard Crosspoint Switch  National Semiconductor SCAN90CP02 Additional Onboard Hardware  LCD to display BERT results

27. 27 Our Recommendation - Option B Reduced cost Ease of implementation All on one printed circuit board

28. 28 Projected Costs 4 x FPGA  Xilinx Spartan IIE FPGA - $50.00 1 x Crosspoint Switch  National Semiconductor SCAN90CP02 - $5.00 4 x Serializer / Deserializer  National Semiconductor DS92LV18 - $16.50 LCD and Misc. Connectors - $50.00 Printed Circuit Board Fabrication - $250.00 Total Projected Cost: $571.00

29. 29 Questions & Comments

30. 30 Work Breakdown Structure

31. 31 Option Comparison FPGASerDesXBARPCBMisc Total Cost Option A Pros: D2SB/DIO5 - $0National DS92LV18 - $16.50National SCAN90 - $5.00~$250~$50$371 Easy setup, LCD included, Relative low cost Cons: May reduce speed, complicated connector layout Option B Pros: Xilinx Spartan IIE - $50National DS92LV18 - $16.50National SCAN90 - $5.00~$250~$50$571 Faster onboard comm., Less noise, smaller board area Cons: Requires more components, complicated pinouts Option C Pros: Xilinx Virtex II - $1000N/A - $0National SCAN90 - $5.00~$250~$50$4,305 Least amount of components, less interconnect, smallest board size Cons: Difficult VHDL implementation, expensive FPGA