1. CMS June 2003 1 TriDAS Update Drew Baden University of Maryland http://www.physics.umd.edu/hep/HTR/hcal_june_2003.pdf USCMS HCAL

2. CMS June 2003 2 HTR Status Rev 1 run Summer 2002 testbeam  Board worked well – all functional requirements met  Big concern on mechanical issues for production oHad a difficult experience with previous board manufacturing Rev 2 produced March 2003  Board production changes: oNew assembler, in-house X-ray, DFM review, QC oGold plated (Rev 1 was white-tin) for better QC  Changes to HTR: oChange from Virtex 1000E FBGA (1.00mm) to Virtex2 3000 BGA (1.27mm) oAdded stiffeners oMoved all SLB/TPG output to front-panel daughterboards oModified Rx refclk scheme (the usual TTC/refclk clocking concerns)  Full 48 channel capability (Rev 1 was “half HTR”)  As of this date, no issues – this board is functioning well

3. CMS June 2003 3 Dual-LC O-to-E VME Deserializers Xilinx XC2V3000-4 Stiffeners 6 SLBs TTC mezzanine HTR Rev 3 (cont)

4. CMS June 2003 4 HTR Rev 3 30 boards delivered April 21  Checkout consisted of oAll systems except connectivity to SLB oFiber links checked out at 1.7Gbaud bit rate (1.6Gbaud is CMS requirement)  Frame clock up to 2.0Gbaud bit rate and it stays synchronized  No BER yet…will do a lab measurement soon  12 boards x 16 links ~200 links(~5% of total) with no problems  Used both onboard crystal oscillator and external clock for REFCLK  Minor adjustments will be needed for front panels, stiffeners, etc.  Will battle test these boards this year oMay synchronous testbeam just completed oJuly testbeam oVertical Slice tests to commence in the fall

5. CMS June 2003 5 Clocks and Synchronization Clocking considerations can be divided into 2 parts:  Deserializers REFCLK: stability critical (80MHz frame rate) oStability: must have a very low jitter – 30 to 40ps pkpk spec oFrequency: TI TLK2501 spec is 100ppm (8kHz) to lock  Measured ~350ppm (30kHz) needed to establish link  LHC variation expected to be few kHz  Once link is established, just needs to be stable (it’s a REFCLK!!!) oPhase: relationship to LHC clock totally irrelevant  Phase critical clock for pipeline synchronization oMust be in phase with LHC clock oJitter spec is very lose – this clock is used inside FPGA for sequential logic

6. CMS June 2003 6 HCAL Clock Fanout HTR clocks provided by a single 9U VME board  Chris Tully/Jeremy Mans from Princeton  Has fiber TTC input Signals fanned out over Cat6 twisted pair:  TTC stream oTo be used by each HTR and by DCC to decode commands & L1A  BC0 oTo be used by SLBs to synchronize TPGs  “40MHz” clock oTo be used by FPGA and SLBs to maintain pipeline  Comes from QPLL  “80MHz” clean clock oTo be used for deserializer REFCLK  Comes from QPLL

7. CMS June 2003 7 Clock Distribution HTR TTC fiber TTC CLK80 BC0 CLK40 distribution to 6 SLBs and to 2 Xilinx Brdcst, BrcstStr, L1A O/E BC0 TTC FPGA.. Test Points for RxCLK and RxBC0.. 80.18 MHz.. TTCrx to Ref_CLK of SERDES (TLK2501) CLK40 CLK80 Princeton Fanout Board TTCrx QPLL HTR Cat6E or Cat7 Cable

8. CMS June 2003 8 TTC receiver - TTCumd General purpose TTC receiver board (TTCumd)  TTCrx ASIC and associated PMC connectors Will be used to receive TTC signal by HTR, DCC, and clock fanout boards No signal receivers!  Copper/fiber receivers must be on the motherboard  Signal driven through TTC connectors Tested successfully by Maryland, Princeton, BU groups Princeton Fanout Card

9. CMS June 2003 9 May Testbeam Setup Lack of a QPLL or decent equivalent – had to improvise:  Front-end used commercial Cypress PLL oMatches GOL 100ps pkpk jitter spec  Fanout card oNo clean 80MHz REFCLK, so provided 2 alternatives:  2xLHC clock from crystal oscillator  High quality clock from HP signal and pulse generators  Jumper selectable on mezzanine cards oNo clean 40MHz system clock  Just used 40MHz output from TTCrx chip anyway

10. CMS June 2003 10 May Testbeam Experience To establish link:  FE oTTC 40MHz clock cleaned up by Cypress “roboclock” chip (Cy7B993) oFE reset signal to GOL  Fanout card oFanout from onboard 80.1576MHz crystal oscillator for REFCLK oFanout TTC 40MHz clock for system clock  HTR oTLK2501 link circuitry always enabled  Result: Fiber 1.6GHz link established ok oNo problem locking – worked every time.

11. CMS June 2003 11 Testbeam Experience (cont) Link stability - VERY PRILIMINARY, STILL STUDYING  Ran 10hr test on 48 fibers o3 x 10 15 bits o20% failed to maintain link oDuring synchronized beam running, sent reset between spills to ensure link  Similar tests at Maryland using TI eval board showed no link errors, similar number of bits sent Curret plan  Study FE →HTR link at FNAL this month oFNAL test stand setup this week  Investigate noise characteristics of H2 environment oH2 is clearly different than FNAL, Maryland and BU experience  Review of HTR and Fanout card oWill learn what we need to do from the above Best guess  All tests in US indicate solid link, but experience in H2 disagree  Probably some kind of new noise component – figure out and correct.

12. CMS June 2003 12 HCAL TPG Nothing new since May Electronics Week TPG under development…  Preliminary FPGA code for TPGs done oLUT for linearization (downloadable), 0.5GeV steps, 255Gev max E T oE to E T and sums over as many as 7 channels  Not implemented in code yet…TBD oMuon window in E oBCID filter algorithm TBD from testbeams oCompression LUTs for output to SLBs  Utilization is ~50% of Virtex2 3000 oWe are confident this chip will be sufficient  Simulation effort under way… Latency issue  See below – we are working on this…

13. CMS June 2003 13 HTR TPG Commissioning 2 Xilinx FPGAs per HTR  3 SLBs per Xilinx  Each mounted on triPMC connectors Will test internal connectivity to SLBs at UMD  For signals and for localbus connections Need a scheme to test HTR/RCT connectivity  Not just electrical! Also includes data integrity SLB Xilinx RCTRCT

14. CMS June 2003 14 HTR/RCT Testing Will build PMC tester card to mount onto HTR  Host to 1 or more Wisconsin RCT Vitesse receiver boards Will run the signals from this RCT tester card back into Xilinx  Using 1 HTR, both FPGAs – one source, one sink – to test sending data from HTR to RCT Will try to engineer 3-SLB test to test single Xilinx → SLB →RCT SLB Xilinx RCT

15. CMS June 2003 15 HTR Production Full contingent of HTRs: 260 boards  Includes 10% spares, 20% spares for parts Full production will begin after:  Testbeam demonstrates I/O works under battle conditions  Successful testing of the 6 SLB daughter card functions  Understanding of how to meet latency issues o We are still some clock ticks short, but firmware is still very immature for the TPG part of the HTR (see slides below) Best guess: fall 2003  There is no reason to hurry other than to finish with the R&D part of the project  Current board design will be final, perhaps some layout adjustments based on conclusion of testbeam effort

16. CMS June 2003 16 Overall Commissioning Schedule Summer 2003 testbeam  Repeat previous test w/production prototype boards Fall 2003 Slice tests  HCAL will join as schedule allows 2003/2004 HCAL burn-in  Continue with firmware development/integration as needed 2004/2005 Vertical Slice and magnet test  We will be ready  All HCAL TriDas production cards involved October 05 beneficial occupancy of USC  Installation of all racks, crates, and cards  We do not anticipate any hardware integration oShould be all firmware / timing / troubleshooting

17. CMS June 2003 17 TPG Latency “ Minimizing the trigger latency” ItemLatency TOF.5 HCAL Optics1 FE (CCA+QIE)8-9 GOL2 Fiber Tx to HTRs18 Deserializer2-3 HTR Alignment6 HTR TPG path5-10 SLB3 TPG Cables4 TOTAL50 - 57 Current total 50 – 57 clocks  Very rough guesses oMany numbers have not been measured Optimizations:  Fiber cables need to be 90m?  HTR firmware needs optimization  Deserializer random latency fix  TPG cables changed to 15m will save 1 tick  Others…main efforts over next 6 months

18. CMS June 2003 18 TPG Path E T comp 7 10 Muon bit Sum Consecutive Time-samples 9 TP 8 QIE-data INPUT LUT Lineariz. and E t E T [9:0] 2 Compression LUT 2 Muon LUT 1 Delay to synchronize with BCID 10 L1 Filter 10 Sum in E T Peak Detection TP_Bypass 1010 2 2 2 Mask & Reset “NO-SHOWER” LUT take care of cases where showers can leak into a cell and incorrectly set the muon bit. BCID BCID avoids to flag as a muon the tail of a more energetic event