1. Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu/~spark Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis Supported by Semiconductor Research Corporation Sumit Gupta Nikil Dutt Mehrdad Reshadi Rajesh Gupta Nick Savoiu Alex Nicolau

2. High Level Synthesis M e m o r y ALU Control Data path d = e - fg = h + i If Node TF c x = a + b c = a < b j = d x g l = e + x x = a + b; c = a < b; if (c) then d = e – f; else g = h + i; j = d x g; l = e + x; Transform behavioral descriptions to RTL/gate level From C to CDFG to Architecture

3. Common Sub-Expression Elimination a = b + c; c = b < c; if (c) d = b + c; else e = g + h; An Example BB 1BB 2 BB 0 d = b + c BB 3 a = b + c e = g + h HTG Representation If Node T F BB 1BB 2 BB 0 d = a BB 3 a = b + c e = g + h After CSE If Node TF

4. New Opportunities for “Dynamic” CSE BB 2BB 3 BB 1 a = b + c BB 6BB 7 BB 5 d = b + c BB 4 BB 8 Speculate Speculative Code Motions employed during Scheduling enable new “Dynamic” opportunities for CSE BB 2BB 3 BB 1 a = dcse BB 6BB 7 BB 5 d = dcse BB 4 BB 8 dcse = b + c BB 0

5. Speculative Code Motions + + If Node TF Reverse Speculation Conditional Speculation Across Hierarchical Blocks _ a b c Hierarchical Task Graph Representation of Control-Data Flow Graph

6. Speculative Code Motions + + If Node TF Reverse Speculation Conditional Speculation Across Hierarchical Blocks _ a b c Hierarchical Task Graph Representation of Control-Data Flow Graph

7. Condition Speculation & Dynamic CSE BB 1BB 2 BB 0 BB 5BB 6 BB 4 a = b + c BB 3 BB 7 d = b + c Conditionally Speculate BB 1BB 2 BB 0 BB 5BB 6 BB 4 a = a' BB 3 BB 7 a' = b + c d = b + c BB 8

8. Condition Speculation & Dynamic CSE BB 1BB 2 BB 0 BB 5BB 6 BB 4 a = b + c BB 3 BB 7 d = b + c BB 1BB 2 BB 0 BB 5BB 6 BB 4 a = a' BB 3 BB 7 a' = b + c d = a' Conditionally Speculate

9. Experimental Setup Have implemented Dynamic CSE along with Speculative Code Motions in the SPARK high- level synthesis framework Have implemented Dynamic CSE along with Speculative Code Motions in the SPARK high- level synthesis framework Takes behavioral description in C as input Takes behavioral description in C as input Produces synthesizable RTL VHDL Produces synthesizable RTL VHDL Experimented with functions from moderately complex industrial designs: Experimented with functions from moderately complex industrial designs: MPEG-1 Prediction Block MPEG-1 Prediction Block Gimp Image Processing Tool Gimp Image Processing Tool

10. DCSE Synthesis Results: Pred0 No CSE With CSE With Dynamic CSE With CSE & Dynamic CSE Delays reduce by up to 40 % Area reduces by up to 35 % Register Usage Reduces ! Delays reduce by up to 40 % Area reduces by up to 35 % Register Usage Reduces !

11. Conclusions Dynamic CSE leads to significant improvements in delay and area – in the range of 40 % Dynamic CSE leads to significant improvements in delay and area – in the range of 40 % Register usage reduces because Register usage reduces because Shorter schedule lengths => shorter variable lifetimes Shorter schedule lengths => shorter variable lifetimes Operation elimination by CSE => fewer variables stored Operation elimination by CSE => fewer variables stored Only one result has to be stored instead of two input variables Only one result has to be stored instead of two input variables Principle of Dynamic CSE extends to Dynamic Copy Propagation et cetera Principle of Dynamic CSE extends to Dynamic Copy Propagation et cetera

12. Thank You