1. Viterbi Decoder: Presentation #1 Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun M1 Overall Project Objective: Design of a high speed Viterbi Decoder Stage 1: 21 Jan. 2004 Project Proposal

2. Status Design Proposal (done) Architecture (in progress) To be done: Floor Plan Gate Level Design Component Layout Chip Layout Spice Simulation of Entire Chip

3. What is Viterbi Decoder?  A processor that implements the Viterbi algorithm  Widely used in digital communication and storage Cellular telephone: convolutional code decoding Magnetic, optical disk drives: channel detector

4. Why Viterbi Decoder  Example : Hard disk drive:  Viterbi algorithm: Take the received signal Find out the most likely input sequence 01000111, 01001111, 01001111, 01000100 GOOD SLOW 01010011, 01001100, 01001111, 01010111

5.  Calculation along the trellis The Viterbi Algorithm  Implementation Architecture Branch Calculation Unit Add Compare Select Unit Maximum Likelihood Path Search Trace FIFOTrace Back Control Unit

6. Schematic Diagram D D … … D D D D DD D D … … ……….. … C0C1C2C3Cn-1Cn ……….. Control Logic Input Output BCU ACS ML Search FIFO & trace back Input_valid Clock Vdd Gnd Output_valid Reset

7. Transistor Estimate Adders 59 x 100 = 5900 2:1 8-bit Multiplexers11 x 96 = 1056 Multipliers16 x 240 = 3840 Registers160 x 15 = 2400 Control Logic Total~14196 Design Goal: High speed Above: No. of components x No. of transistors 1000

8. Other Ideas  Equalizer  Fast Fourier Transform  Adaptive Filter  Auto-Regressive Filter

9. Questions?