1. Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects
Lei He, Andrew B. Kahng*, Kingho Tam, Jinjun Xiong
EE Department, University of California, Los Angeles
*ECE Department, University of California, San Diego
VMIC-2004, Waikoloa, October 2, 2004

2. CMP and Fill
Dishing and erosion  require dummy fill insertion for metal density and CMP uniformity

3. Fill Design Rules Lower and upper bounds on fill dimensions
Minimum fill spacing rules
Between fills
Between fill and functional feature
Crude “coverage” bounds (e.g., between 30-70% density)
Saddle point of weak filling rules and weak filling tools

4. Fill Pattern Fill pattern inserted between “active” interconnects
Blue: active interconnect
Gray: dummy fill
Subset of potential fill patterns:
Rectangular shapes
Isothetic (aligned with axes)
Characterized by:
Number of rows (M=5)
Number of columns (N=3)
Series of widths (W)
Series of lengths (L)
Series of horizontal spacings (Sx)
Series of vertical spacings (Sy)

5. Fixed-Dissection Fill Synthesis
Fixed set of w  w windows, each partitioned into r2 tiles
n  n layout has nr/w  nr/w overlapping fixed dissections
Find the amount of fill within each tile such as to:
Minimize window density variation [Kahng et. al., TCAD’02]
Minimize total amount of added fill [Wong et. al., DAC’00]
w/r
Overlapping windows w n
tile

6. Performance-Driven Fill (DAC-2003)
Dummy fill increases capacitance, delay, crosstalk
 Insert fill where layout and timing can best tolerate it
Full solution: Timing path driven, multi-layer aware
This work addresses: How much can the fill pattern matter?

7. Driving Questions
How much does fill affect coupling and total capacitance?
How much do dishing and erosion affect interconnect performance?
Is this impact on par with that of device variability?
What QOR loss is incurred by CMP-oblivious interconnect design?
Where this is leading:
CMP-aware fill pattern synthesis
CMP-aware fill and interconnect synthesis
CMP-and fill-aware routing
 CMP modeling drives performance analysis, layout signoff

8. Introduction and study goals
Outline
Introduction and study goals
Impact of fill insertion and fill patterns
Impact of dishing/erosion on RC parasitics
Impact on interconnect design
Bandwidth optimization
Delay minimization
CMP variation vs. random device variation
Conclusions
Note: This talk = outline of methodology and analysis framework to drive full-chip place/route

9. Fill Pattern Concerns
How much can fill patterns affect interconnect cap?
What is the range of capacitance impact across “equivalent” fill patterns?
“Equivalence” is with respect to multi-layer CMP modeling, per-feature defocus budgeting, etc.

10. Distribution Characteristic Function
Given a total budget (e.g., width, length, spacing), distribute the budget to a given series (e.g., widths) via a Distribution Characteristic Function
Uniform
Linear increasing
Linear decreasing
Convex triangular

11. DCF for Fill Pattern Exploration
Different DCF combinations for width, length, and spacing series result in different fill patterns
Facilitates systematic exploration of wide range of fill patterns
Enumeration is infeasible
Runtime and flexibility of capacitance extraction are another limit

12. Simulation Experiments: Setup
Technology
90nm
65nm
Interconnect
Interm.
Global
Min-width (= min-spacing)
0.23
0.34
0.16
0.24
Metal thickness (t)
0.36
0.67
0.27
0.50
ILD thickness
0.32
0.60
0.45
Interconnect models: Microstripline (G-M), Stripline (G-M-G)
Intermediate, Global interconnects at 90nm, 65nm nodes
Width (w) = minimum width
Spacing (s) = 10X minimum spacing
Length (l) = 2000um
Metal density requirement between active interconnects = 50% (strict)
Three types of DCF for fill pattern exploration
Uniform, Linear increasing, Linear decreasing
All fills are floating
QuickCap employed for capacitance extraction

13. G-M-G, 90nm, Intermediate Interconnect
Fill increases Cc significantly (Nominal Cc = 0.06fF)
minCc/nomCc = 4.7x, maxCc/nomCc = 26.4x
Fill increases Cs moderately (Nominal Cs = 86.33fF)
minCs/nomCs = 1.043x, maxCs/nomCs = 1.092x

14. G-M-G, 90nm, Intermediate Interconnect
Different fill patterns result in very large Cc variation
(maxCc – minCc)/nomCc = 21X
Different fill patterns result in slight Cs variation
(maxCs – minCs)/nomCs = 4.9%

15. G-M-G, 90nm, Intermediate Interconnect
Possible design guidelines for Cc minimization
If the number of fill rows (M) is fixed, use as many fill columns (N) as possible

16. G-M-G, 90nm, Intermediate Interconnect
Possible design guidelines for Cc minimization
If the number of fill columns (N) is fixed, use as few fill rows (M) as possible

17. G-M-G, 90nm/65nm, Intermediate/Global Interconnects
The left two are 90nm; the right two are 65nm
The top two are for intermediate interconnect; the bottom two are for global intermediate interconnect
We have similar observations.
Note, these are for stripline structures.

18. G-M, 90nm/65nm, Intermediate/Global Interconnects
These are for micro-stripline structures.
Again,
The left two are 90nm; the right two are 65nm
The top two are for intermediate interconnect; the bottom two are for global intermediate interconnect
We can see similar observations still hold.

19. Mini-Conclusion on Fill Insertion and Fill Pattern
Fill insertion can dramatically increase Cc and Cs over their respective nominal values
G-M-G, 90nm, Intermediate: Cc 26X, Cs 9%
Cc and Cs varies significantly across different fill patterns
G-M-G, 90nm, Intermediate: Cc 21X, Cs 5%
Useful fill pattern design guidelines may be possible, e.g.:
If the number of fill rows (M) is fixed, use as many fill columns (N) as possible
If the number of fill columns (N) is fixed, use as few fill rows (M) as possible
Additional studies needed with tighter wire pitches, more exhaustive analysis of fill patterns, etc.

20. Introduction and study goals
Outline
Introduction and study goals
Impact of fill insertion and fill patterns
Impact of dishing/erosion on RC parasitics
Impact on interconnect design
Bandwidth optimization
Delay minimization
CMP variation vs. random device variation
Conclusions

21. Modeling of Dishing and Erosion
Dishing/erosion model [Tugbawa et al., CMP-MIC 1999]
Affects only metal thicknesses
Is a function of metal density and metal width
We assume
Metal density requirement between active interconnect = 50% with fill insertion
Rectangular shape used to approximate the concave shape from dishing

22. Impact on Global Interconnect Resistance
Resistance variation is significant
From 43.73% to %
Rf due to dishing/erosion is large: less cross-section
As width (w) grows, R variation also increases
90nm: 43.73% to 63.16%
65nm: 74.58% to %
Width w
(μm)
Nominal Ro (kΩ)
Real Rf
(kΩ)
90nm technology
0.34
39.2
56.35 (+43.73%)
3.69
3.6
5.49 (+54.03%)
6.70
2.0
3.20 (+63.16%)
65nm technology
0.24
78.0
(+74.58%)
2.61
7.1
13.50 (+90.32%)
4.75
3.9
8.02 ( %)

23. Impact on Global Interconnect Capacitance
Three scenarios:
S1: Interconnect with nominal value
S2: Interconnect affected by dishing/erosion, WITHOUT fill insertion
S3: Interconnect affected by dishing/erosion, WITH fill insertion
QuickCap is used for capacitance extraction
Coupling Cc, total Cs
Fill pattern is chosen that results in minimum Cc

24. Impact on Global Interconnect Capacitance
(Eye chart omitted)
Dishing and erosion have comparatively smaller impact on capacitance
The fact of fill insertion itself has much larger impact on capacitance

25. Mini-Conclusion on Dishing/Erosion Impact
Dishing and erosion significantly increase interconnect resistance
Dishing and erosion impact on capacitance is ignorable
Is this really the case?
Any such assessment is design- and methodology- dependent
Fill insertion has much larger impact than dishing/erosion on capacitance

26. Introduction and study goals
Outline
Introduction and study goals
Impact of fill insertion and fill patterns
Impact of dishing/erosion on RC parasitics
Impact on interconnect design
Bandwidth optimization
Delay minimization
CMP variation vs. random device variation
Conclusions

27. Interconnect Design Concerns
How do CMP effects change conventional (CMP-oblivious) interconnect design ?
How do we take CMP effects into account for a better (CMP-aware) design flow?
Compared to random device variation, does CMP-induced variation really matter (e.g., should the EDA vendors focus on Device-aware or on CMP-aware analysis and circuit optimization)?

28. Experiment Setup Interconnect design for parallel buses
Interconnect sizing (w) and spacing (s)
Buffer insertion (k) and sizing (h)
Figure-of-merit
Bandwidth: BW = #bits/delay [Pamunuwa et al., ISCAS02]
Delay
Two problem formulations
Bandwidth optimization
Variables: interconnect (width, space, bits), buffer (number, size)
Constraint: total bus area is fixed
Delay minimization
Variables: interconnect (width, space), buffer (number, size)
Constraints: total bus area and interconnect bits are fixed
Solution N (CMP-oblivious) vs. Solution C (CMP-aware)

29. BW Optimization Impact from dishing and erosion only
BW optimization leads to thin, dense bus lines
Wrong metric?
Small line space prohibits dummy fill insertion
Technology
Layer
Solution N
Solution C
w (μm)
s (μm)
est. BW (Tb/s)
act. BW (Tb/s)
# buf
buf size
act. Δ BW (%)
Δ k (%)
Δ h (%)
Total Buffer Area Unconstrained
90 nm
global
0.335
0.931
0.857 3
168
0.233
-7.74
interm
0.225
4.38
3.70 1 96
0.804
-15.6
65 nm
0.238
0.945
0.840 4
124
0.357
-10.5
0.16
4.46
3.39 71
3.24
100
-21.1
Total Buffer Area Constrained to 50%
0.893
0.821 2
126
0.889 82
Animations:
BW maximization prefers minimum spacing (and width). Therefore CMP impacts only come from dishing and erosion.
Without considering CMP can cause up to 24% over-estimation in BW.
Considering CMP during design can gain up to 3.24% in BW.
The gain comes from more suitable buffer insertion for CMP-perturbed RC.
When total buffer area is constrained, both CMP-aware and CMP-unaware design maximizes the use of buffer resource until it reaches the bound. Therefore both designs give the same buffer insertion solution and hence CMP-aware design achieves no improvement.

30. Delay Minimization Impacts from dishing, erosion and fill
Assuming optimum fill pattern
Wires tends to be wider and sparser
Technology
Layer
Solution N
Solution C
w (μm)
s (μm)
est. delay (ps)
act. delay (ps)
# buf
buf size
act. Δ delay (%)
Δ k (%)
Δ h (%)
Total Buffer Area Unconstrained
90 nm
global
2.68
1.34
61.4
69.5 1
510
3.02
1.01
-1.16
1.96
interm
1.35
0.675
27.7
31.8
264
-0.943
-17.8
65 nm
2.14
0.95
83.9
95.8 2
404
-0.522
-13.1
0.96
0.48
34.0
43.0
190
0.8
0.64
-2.56
-36.8
Total Buffer Area Constrained to 50%
2.01
66.2
73.5
255
84.1
100
-0.900
Animations
Wire spacing is much larger due to delay minimization, therefore CMP impacts include dishing, erosion and dummy fill.
Delay under-estimation can be as large as 26% when CMP is not considered.
CMP-aware design achieves up to 2.56% improvement over CMP-unaware design.
The gain comes from both using a different width/spacing combination and more suitable buffer insertion.
When buffer area is constrained, the gain from CMP-aware design is limited when buffer resource max out.

31. CMP Variation vs. Random Device Variation
Device random variation
An important manifestation of process variation
CMP variation vs. device random variation?
Random device variation modeling
Buffer output resistance has Gaussian distribution
Standard deviation = 15% of mean value
Experiment setup
BW optimization: device-aware vs. CMP-aware
Device-aware: 0.176% improvement over device-oblivious
CMP-aware: 0.295% improvement over CMP-oblivious
Delay minimization: device-aware vs. CMP-aware
Device-aware: % improvement over device-oblivious
CMP-aware: % improvement over CMP-oblivious
CMP induced variation is at least as important as random device variation!
Intrinsic delay and input capacitance comparatively insensitive to Leff variation, therefore are not considered variable

32. Mini-Conclusion on Interconnect Design
CMP-oblivious design’s nominal values overestimate interconnect bandwidth
Up to 24%
CMP-oblivious design’s nominal values underestimate interconnect delay
Up to 26%
CMP-aware design can achieve up to 3% improvement for both BW and delay, compared to the “adjusted” CMP-oblivious design
“Adjusted” = CMP effects considered
CMP induced variation is as important as random device variation (assuming ITRS bounds )

33. Introduction and study goals
Outline
Introduction and study goals
Impact of fill insertion and fill patterns
Impact of dishing/erosion on RC parasitics
Impact on interconnect design
Bandwidth optimization
Delay minimization
CMP variation vs. random device variation
Conclusions

34. Design without considering these variations
Conclusions
Dummy fill can cause very large coupling capacitance variation w.r.t. nominal
Dishing and erosion cause substantial resistance increase, but have limited impact on coupling
Design without considering these variations
Overestimates interconnect bandwidth
Underestimates interconnect delay
CMP-aware design can improve design quality
Ongoing directions
Integration of multi-layer CMP modeling into flow
CMP-aware fill pattern synthesis, then single-interconnect wire and buffer sizing, then full routing