1. Tunneling Devices Dane Wheeler April 19, 2005 Dane Wheeler April 19, 2005 EE666 – Advanced Semiconductor Devices

2. Tunneling Devices Dane Wheeler April 19, 2005 Dane Wheeler April 19, 2005 EE666 – Advanced Semiconductor Devices

3. OutlineOutline MotivationMotivation Band-to-Band TunnelingBand-to-Band Tunneling Device ProposalsDevice Proposals Fabrication TechniquesFabrication Techniques Notre Dame DevicesNotre Dame Devices ConclusionsConclusions MotivationMotivation Band-to-Band TunnelingBand-to-Band Tunneling Device ProposalsDevice Proposals Fabrication TechniquesFabrication Techniques Notre Dame DevicesNotre Dame Devices ConclusionsConclusions

4. MotivationMotivation Scaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effectsScaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effects Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETsPower Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs Design Flexibility: Circuits can be made with fewer devicesDesign Flexibility: Circuits can be made with fewer devices Scaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effectsScaling: some proposed tunneling field effect transistor (TFET) designs do not suffer from short channel effects Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETsPower Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs Design Flexibility: Circuits can be made with fewer devicesDesign Flexibility: Circuits can be made with fewer devices

5. Obligatory Moore’s Law Reference http://www.intel.com/research/silicon/mooreslaw.htm human brain in 2012?

6. What’s so great about a tunneling device? Lower sub-threshold swing can allow for lower operating voltages to be usedLower sub-threshold swing can allow for lower operating voltages to be used Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc.Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc. Leads to chips that consume less powerLeads to chips that consume less power Lower sub-threshold swing can allow for lower operating voltages to be usedLower sub-threshold swing can allow for lower operating voltages to be used Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc.Negative differential resistance (NDR) properties can be exploited to create simpler designs for bi-stable circuits, differential comparators, oscillators, etc. Leads to chips that consume less powerLeads to chips that consume less power

7. TunnelingTunneling Tunneling is a quantum mechanical phenomenon with no analog in classical physicsTunneling is a quantum mechanical phenomenon with no analog in classical physics Occurs when an electron passes through a potential barrier without having enough energy to do soOccurs when an electron passes through a potential barrier without having enough energy to do so Tunneling is a quantum mechanical phenomenon with no analog in classical physicsTunneling is a quantum mechanical phenomenon with no analog in classical physics Occurs when an electron passes through a potential barrier without having enough energy to do soOccurs when an electron passes through a potential barrier without having enough energy to do so

8. (Esaki) Tunnel Diode (TD) Simplest tunneling deviceSimplest tunneling device Heavily-doped pn junctionHeavily-doped pn junction –Leads to overlap of conduction and valence bands Carriers are able to tunnel inter-bandCarriers are able to tunnel inter-band Tunneling goes exponentially with tunneling distanceTunneling goes exponentially with tunneling distance –Requires junction to be abrupt Simplest tunneling deviceSimplest tunneling device Heavily-doped pn junctionHeavily-doped pn junction –Leads to overlap of conduction and valence bands Carriers are able to tunnel inter-bandCarriers are able to tunnel inter-band Tunneling goes exponentially with tunneling distanceTunneling goes exponentially with tunneling distance –Requires junction to be abrupt ECEC EVEV EFEF

9. Band-to-Band Tunneling in a Tunnel Diode ECEC EVEV EFEF I V (a) (b) (c) (d) (e) (a) (b) (c) (d) (e)

10. Figures of Merit I V Peak current 100 kA/cm 2 Peak-to-Valley Ratio (PVR)

11. Bi-stable Configuration I V D2D2 D1D1 X V X1X1 X2X2

12. TD Differential Comparator M1M1 M2M2 I TAIL  V EE V CC M4M4 M3M3 V OUT RLRL I1I1 I2I2 RLRL CK V IN D1D1 D3D3 D2D2 D4D4 X

13. Direct vs. Indirect Tunneling Direct Indirect Indirect materials require phonons to tunnel, thus reducing the probability of a tunneling event

14. Tunnel Current Expressions

15. Lateral TFET Proposed by our own Qin ZhangProposed by our own Qin Zhang Can theoretically beat 60 mV/decade sub- threshold swingCan theoretically beat 60 mV/decade sub- threshold swing Proposed by our own Qin ZhangProposed by our own Qin Zhang Can theoretically beat 60 mV/decade sub- threshold swingCan theoretically beat 60 mV/decade sub- threshold swing S D G ox n + Sip + Si x y BOX LW t ox t Si

16. Lateral TFET Off State On State

17. Another Lateral TFET Proposed by A. Zaslavsky in SOI, although original idea from ShockleyProposed by A. Zaslavsky in SOI, although original idea from Shockley Gate placed on top of depletion regionGate placed on top of depletion region Proposed by A. Zaslavsky in SOI, although original idea from ShockleyProposed by A. Zaslavsky in SOI, although original idea from Shockley Gate placed on top of depletion regionGate placed on top of depletion region

18. More about AZ TFET

19. Double Lateral TFET Acts as back-to-back TD pair at 0 gate biasActs as back-to-back TD pair at 0 gate bias Gate bias of either polarity will break tunneling conditionGate bias of either polarity will break tunneling condition Acts as back-to-back TD pair at 0 gate biasActs as back-to-back TD pair at 0 gate bias Gate bias of either polarity will break tunneling conditionGate bias of either polarity will break tunneling condition

20. Fabrication Techniques As mentioned earlier, heavily-doped, abrupt junctions are neededAs mentioned earlier, heavily-doped, abrupt junctions are needed Can be obtained using several different methodsCan be obtained using several different methods –Ion implantation –Rapid thermal diffusion –Molecular beam epitaxy –Laser diffusion As mentioned earlier, heavily-doped, abrupt junctions are neededAs mentioned earlier, heavily-doped, abrupt junctions are needed Can be obtained using several different methodsCan be obtained using several different methods –Ion implantation –Rapid thermal diffusion –Molecular beam epitaxy –Laser diffusion

21. Doping by Rapid Thermal Processor Approach: Rapid thermal diffusion Spin-on diffusants 100 mm wafers IC-compatible processes Modular Process Technology RTP-600S

22. Proximity Rapid Thermal Diffusion

23. Rapid Thermal Diffusion Transient-enhanced diffusion effects dominate, increasing diffusivity of dopants

24. Ion Implantation

25. Simulated Built-in Field

26. Simulated Band Diagram

27. First TDs from Rapid Thermal Diffusion

28. TDs with Oxide Window Process First demonstration of tunnel diodes on high resistivity 1 – 5 k  cm substrates Enables microwave characterization

29. ConclusionsConclusions Tunnel diodes are expected to add another node in the roadTunnel diodes are expected to add another node in the road Three-terminal tunnel devices could add several nodes at the end of CMOS-scalingThree-terminal tunnel devices could add several nodes at the end of CMOS-scaling Challenges facing TFETs are more practical than theoreticalChallenges facing TFETs are more practical than theoretical –Lithography, SOI process optimization Tunnel diodes are expected to add another node in the roadTunnel diodes are expected to add another node in the road Three-terminal tunnel devices could add several nodes at the end of CMOS-scalingThree-terminal tunnel devices could add several nodes at the end of CMOS-scaling Challenges facing TFETs are more practical than theoreticalChallenges facing TFETs are more practical than theoretical –Lithography, SOI process optimization