1. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 0.1 Process: Focus on Change Challenges & Directions Technology Paradigm Shifts Market Segment Semiconductor Process Design Methodology Electronic Design Automation Research

2. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 0.2 Technology Trends 19982003 Feature Size Interconnect Delays and Signal Integrity Clock Freq Power & Signal Integrity Device Count 19982003 Designer Productivity 19982003

3. EDA Roadmap Taskforce Report Draft 2 2/9/99 1u.8u.6u.35u.25u.18u.13u.1u Clock Freq (MHz) 10 100 1000 10000 Process Actual Freq Design chip Process Min Geometry Based on Information provided by Shakhar Borkar, Intel Figure 0.3 Design Pushing Frequency Through Architecture and Circuit Changes

4. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 0.4 Power Rises Sharply 1u.8u.6u.35u.25u.18u.13u.1u 1 10 100 1000 Process Min Geometry.1 AMPS chip Based on Information provided by Shakhar Borkar, Intel

5. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 1.1 Target Chip Data Sheet Design Size: Total Transistors200 million Total Logic Transistors50 million Chip I/Os4000 Wiring levels8 Scaling: Target Process for Microprocessors 100nm (2003 Starts for 2005 Ship) Chip Size520 mm 2 Frequency: Local Clock Freq.3.5 GHz 3rd Harmonic = 9GHz Slew rate = 150Ghz Chip Statistics Chip I/Os:4000 Wiring levels8 Total Interconnect length2840 m/chip

6. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 1.2 Global and Local Delays vs. Gate-Device Delays Delay (ns).01.1 1 Process Minimum Geometry (nm) 130 100 70 Device Delay 1 mm Interconnect 1 cm Buffered Interconnect

7. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 1.3 Taskforce Objective Taskforce objectivelarger chips fewer engineersmore detail report identifiessemiconductor processing, design methodologyelectronic design automation The Taskforce objective is to find approaches to design larger chips with fewer engineers while being concerned about more detail. This report identifies enhancements and modifications to semiconductor processing, design methodology and electronic design automation that the Taskforce feels is necessary to reach this objective.

8. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 2.1 Growth in Active Capacitance Process Minimum Geometry (nm) 13010070.1 1 Active C nf/mm2 Based on Information provided by Shakhar Borkar, Intel

9. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 2.2 More Supply Current Relative Process Minimum Geometry (nm) 13010070 1 2 3 Frequency 1 2 3 Densit y 1 2 3 Power Based on Information provided by Shakhar Borkar, Intel

10. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 2.3 Power / Voltage = Current Process Minimum Geometry (nm) 13010070 10 100 1000 Power (watt).1 1 10 Vcc (volt) 10 100 1000 Current (Amp) Based on Information provided by Shakhar Borkar, Intel

11. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 2.4 Increased Power / Current: Taskforce Recommendations Semiconductor Process Changes Required for Increased Power –Additional Metal Layers for Power Planes –Additional Metal Layers for Shielding –On Chip Decoupling Capacitors Power Management Design Methodology –Increase Usage of Gated Clocks –Staggered Clock –Self Timed and Asynchronous Design Design Automation Required for Increased Power –Early Prediction of Power –Self-Inductive and Mutual-Inductive Effects to Signal Line Avoidance Software. –Power Dependent Timing Verification

12. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 3.1 Gate / Interconnect Delay

13. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 3.2 Delay and Signal Integrity Data Gate Delay 3ps On Chip Parameter Variability+/-10% Average Interconnect Delay12ps Time of Flight 5ps/mm Interconnect Resistance100 ohms/mm Self Inductance Signal Lines 0.5nh / mm Mutual Inductance signal to signal 0.3nh /mm Crosscap 0.2pf/mm Crosscap to Signal lines.6 Cinterconnect / Ctotal Reflections Non--terminated long routes above 9Ghz RF antenna 2.5mm

14. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 3.3 Delay Variation Contributed by A Kahng

15. EDA Roadmap Taskforce Report Draft 2 2/9/99 a b ff A B FF............ Figure 3.4 Signal Interrelationships

16. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 3.5 Signal Integrity and Delay Uncertainty: Taskforce Recommendations Semiconductor Process Changes Required for Signal Integrity and Delay Uncertainty –Additional Metal Layers for Shielding –Low mutual capacitance and low mutual inductance between signals including power Signal Integrity Design Methodology –Hierarchical Design that is Interconnect Centric –Staggered Signals Design Automation Required for Signal Integrity –Physical Design that is Signal Integrity Aware –Multi-Port Delay Models –Multi-Path Timing Analyzer –Interconnect Centric Design Tools which emphasize High Level Physical Design.

17. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 4.1 Guiding Principles Avoid problems Verify once Interconnect centric design Tether design changes

18. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 4.2 Meet in the Middle Design Approach After Architecture Full Chip Layout Forecast Block Specifications Create Blocks Actively Avoid Problems Add Shielding Add Buffers Build / Backannotate Models Verify Block Verify Chip Using Models

19. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 4.3 Interconnect Centric Design System MODEL BUILDER CHIP DESIGN LIBRARY / PROTOTYPES/ GENERATORS/EXPERIENCE ARCHITECTURE MICRO-ARCHITECTURE TAPEOUT FORECASTING VERIFICATION

20. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 4.4 Forecasting Budgets / Specifications Power Distribution Built -in-Test Dominant Signal (Such As Clock and Reset) Block Delay Distribution Signal Integrity Soft Error Control Area / Pinout Function Audit Design vs. Budget

21. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 4.5 Automated Model Builder Estimates Experience History Intellectual Property Generators Prototyping Model Building In-place Models Including Interconnection Backannotate Physical Design Characteristics Full Range of Design Parameters

22. EDA Roadmap Taskforce Report Draft 2 2/9/99 Fig 5.1 Test Cost Impact on Product Pricing

23. EDA Roadmap Taskforce Report Draft 2 2/9/99 Fig 5.2 Yield Loss due to Guard Banding

24. EDA Roadmap Taskforce Report Draft 2 2/9/99 Fig 5.3 Cost Per Burn-in Socket Position

25. EDA Roadmap Taskforce Report Draft 2 2/9/99 Fig 5.4 Time to Market and Volume Increasing Time to Market Time to Volume

26. EDA Roadmap Taskforce Report Draft 2 2/9/99 Fig 5.5 Temperature and Voltage Stress Identifies Faulty Behavior 23 27 31 35 11010090807060504030 Temperature (deg. C) 3.72.52.93.3 20 30 40 50 VDD Voltage (V) Latch-latch minimum delay (ns) Source: Sematech “Test Methods” Study Good device Delay test failures Good device Delay test failures Delay vs. VDD Voltage: 5 delay fails, 1 control Temperature vs. Delay: 2 delay fails, 1 control

27. EDA Roadmap Taskforce Report Draft 2 2/9/99 Fig 6.1 Current Systems Tool 1 Database Tool 2 Database Interchange Format 1 Xlator 1Tool 3 Database Interchange Format 2 Xlator 2Tool 4 Database Interchange Format 3

28. EDA Roadmap Taskforce Report Draft 2 2/9/99 Database Tool 1 CO Interface Database Tool 2 CO Interface Database Tool 3 CO Interface Database Tool 4 CO Interface Fig 6.2 Component Object Systems

29. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 7.1 Process Modifications Power Delivery Power and Ground Planes On chip and/or On MCM Bypass Capacitors Signal Integrity Assurance Shielding Low mutual capacitance and mutual inductance materials

30. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 7.2 New Design Methodologies Signal Integrity Design Methodology Meet-at-the-full-chip level Design Approach Hierarchical Design that is Interconnect Centric Staggered Signals and Asynchronous Logic Rules Based Design Constraints Top Down Forecasting Bottom up Model Building

31. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 7.3 Interconnect Centric EDA MODEL BUILDER CHIP DESIGN LIBRARY / PROTOTYPES/ GENERATORS/EXPERIENCE MICRO-ARCHITECTURE FORECASTING VERIFICATION

32. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 8.1 CMOS Charge is Decreasing

33. EDA Roadmap Taskforce Report Draft 2 2/9/99 Figure 8.2 Soft Errors in CMOS and SOI