1. CSE 140 Discussion Section Midterm #2 Review Mingjing Chen

2. Flip-Flops Conversion Implement a JK flip-flop with a SR flip-flop and a minimal AND-OR-NOT network. S R Q Q’ Combinational logic J K JK flip-flop Solve the combinational logic design problem S = f 1 (J, K, Q) R = f 2 (J, K, Q)

3. Flip-Flops Conversion How to attain the specification of the combinational circuit? SRQQ’ 00Q prev Q’ prev 0101 1010 11 S = f 1 (J, K, Q) R = f 2 (J, K, Q) JKQQ’ 00Q prev Q’ prev 0101 1010 11 Q prev JK QSR 0000 0011 0100 0110 1001 1011 1101 1110 Truth table for combinational logic 0 x x 0 x 0 0 x 0 1 1 0 1 0 0 1

4. Flip-Flops Conversion JKQ prev QSR 000 0 0011 0100 0110 1001 1011 1101 1110 Truth table for combinational logic 0 x x 0 x 0 0 x 0 1 1 0 1 0 0 1 0011 x00x 00011110 0 1 JK Q prev Kmap for S S = J Q’ prev xx00 0110 00011110 0 1 JK Q prev Kmap for R R = K Q prev S R Q Q’ K J

5. Sequential Circuit Design A state machine is described by the following state equations. (1). Write the state table. 2-bit states: Q 1, Q 0 1 input: x 1 output: y XQ1(t)Q0(t)Q1(t+1)Q0(t+1)y 000001 001101 010010 011111 100101 101011 110100 111011

6. Sequential Circuit Design Design the system with two JK flip-flops and a minimal AND-OR-NOT network. XQ1(t)Q0(t)Q1(t+1)Q0(t+1)J1K1J0K0y 000 00 1 001101 010010 011111 100101 101011 110100 111011 0X 1X x1 x0 1X 0X x0 x1 0X x1 1X x0 0X x0 0X x0

7. Sequential Circuit Design XQ1(t)Q0(t)J1K1J0K0y 0001 0011 0100 0111 1001 1011 1100 1111 0X 1X x1 x0 1X 0X x0 x1 0X x1 1X x0 0X x0 0X x0 xx01 xx10 00011110 0 1 Q1Q0 X Kmap for J1 J 1 = X’Q 0 +XQ 0 ’ 01xx 10xx 00011110 0 1 Q1Q0 X Kmap for K1 K 1 = X’ Q 0 ’+X Q 0 0xx0 1xx0 00011110 0 1 Q1Q0 X Kmap for J0 x00x x01x 00011110 0 1 Q1Q0 X Kmap for K0 J 0 = X’Q 1 K 0 = X’ Q 1 ’ 0111 0111 00011110 0 1 Q1Q0 X Kmap for y y = Q 1 ’+Q 0

8. Timing Circuit implemented using two T flip-flops and a D flip-flop. Timing characteristics:  T flip-flop: clock-to-Q maximum delay tpcq = 2ns clock-to-Q minimum delay tccq = 1.8ns setup time tsetup = 1ns hold time thold = 1.5ns  D flip-flop: clock-to-Q maximum delay tpcq = 2.5ns clock-to-Q minimum delay tccq = 2.3ns setup time tsetup = 2.5ns hold time thold = 2ns  NAND gate: propagation delay tpd = 1ns contamination delay tcd = 0.8ns  Inverter: propagation delay tpd = 0.5ns contamination delay tcd = 0.3ns

9. Timing TQ TQ DQ How many paths?

10. Timing TQ TQ DQ 3 paths P1 P2 P3

11. Timing What is the maximum clock frequency of this circuit? P1: tpcq(D) + tpd(NAND) + tsetup(T) <= clock cycle P2: tpcq(T) + tpd(NOT) + tsetup(D) <= clock cycle P3: tpcq(T) + tpd(NAND) + tsetup(T) <= clock cycle 2.5 + 1 + 1 <= clock cycle 2 + 0.5 + 2.5 <= clock cycle 2 + 1 + 1 <= clock cycle Min cycle = 5 ns  max f = 1 / min cycle = 200 MHz

12. Timing what is the maximum clock skew that the circuit can tolerate before it might experience a hold time violation? P1: tccq(D) + tcd(NAND) >= thold(T) + skew P2: tccq(T) + tcd(NOT) >= thold(D) + skew P3: tccq(T) + tcd(NAND) >= thold(T) + skew 2.3 + 0.8 >= 1.5 + skew 1.8 + 0.3 >= 2 + skew 1.8 + 0.8 >= 1.5 + skew Max skew = 0.1ns

13. Decoder & MUX three-input Boolean function f(a, b, c) = ∑Pm(1, 2, 4, 7) + ∑ Pd(3) 01x1 1010 00011110 0 1 ab c f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c)

14. Decoder & MUX Implement the function using a minimal network of 2:4 decoders and OR gates f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’b’c + a'bc’ + abc + ab’c’ 0 1 2 3 s1s1 s0s0 0 1 2 3 s1s1 s0s0 In c a b a b If inverter is not allowed f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’(b+c)+a(b+c)’+bc 0 1 2 3 s1s1 s0s0 0 1 2 3 s1s1 s0s0 In c a b 1 1 c b

15. Decoder & MUX Implement the function using a minimal network of 4:1 multiplexers. f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) = a’b’c + a'bc’ + abc + ab’c’ 0 1 2 3 s1s1 s0s0 a b Out c c’ c

16. Decoder & MUX Implement the function using a minimal network of 2:1 multiplexers f = a’c+a’b+bc+ab’c’ = af(1, b, c) + a’f(0, b, c) = a(bc+b’c’) + a’ (b+c) a 1 0 s b 1 0 s c c’ b 1 0 s 1 c